Lead STA Engineer

ACL Digital; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

ACL Digital is hiring for Static Timing Analysis roles across Bangalore, Hyderabad, and Chennai. The positions require hands-on VLSI timing closure expertise and experience with PrimeTime, Tempus, and QRC on advanced finFET nodes.

Join a dynamic VLSI team focused on full-chip timing signoff, STA analysis, and ECO-driven PPA improvements, while mentoring junior engineers in a high-performance environment.

Qualifications

• Hands-on STA and signoff experience.
• Experience with industry-standard STA tools on advanced nodes.
• Proven track record on finFET nodes.

Responsibilities

• Full-Chip Timing Closure: own and drive timing signoff from synthesis to tapeout across modes and corners.
• STA & Analysis: execute setup, hold, recovery/removal, clock gating, and async path analysis.
• Advanced Effects: resolve cross-talk, noise, derates, and variation in 7nm/5nm/3nm nodes.
• ECO Closure: lead timing ECO strategies for minimal PPA impact.
• Methodology & Quality: enforce best practices and mentor junior/mid STA engineers.

Skills

STA tools

Timing analysis

Signoff

Cross-Node timing

Education

BE/B.Tech in ECE or related

Tools

PrimeTime

Tempus

QRC

Job description

WE ARE HIRING | Static Timing Analysis (STA) Roles at ACL Digital!

Are you passionate about tackling timing challenges on complex, advanced-node SoCs? ACL Digital is expanding its VLSI team across Bangalore, Hyderabad, and Chennai!

We are looking for hands-on, high-performing VLSI professionals to join our timing closure team:

Open Roles

Locations: Bangalore / Hyderabad / Chennai

Key Responsibilities (Lead Role)

• Full-Chip Timing Closure: Own and drive timing signoff for complex SoCs across all modes and corners from synthesis through PnR to tapeout.
• STA & Analysis: Execute setup, hold, recovery/removal, clock gating, and async path analysis.
• Advanced Effects: Resolve issues related to cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects in 7nm / 5nm / 3nm nodes.
• ECO Closure: Lead timing ECO strategies for minimal PPA impact.
• Methodology & Quality: Drive implementation vs. signoff correlation, enforce best practices, and mentor junior/mid-level STA engineers.

Key Requirements

• B.E/B.Tech/M.E/M.Tech in ECE / Electrical / VLSI / Microelectronics.
• Hands-on expertise with industry-standard STA and signoff tools (PrimeTime, Tempus, QRC, etc.).
• Proven track record on advanced finFET nodes.