Sr. Tech Lead SRAM ROM Expert

NXP Semiconductors; Bengaluru; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

NXP Semiconductors NV in Bengaluru seeks a Senior Memory Architect to lead next-generation SRAM/ROM memory architectures and memory IP strategy. You will own roadmaps, collaborate across circuit, design, and process teams, and drive optimization for PPA, reliability, and yield through silicon validation and production.

The role requires 10+ years in memory development, deep CMOS memory knowledge, and a strong track record of silicon delivery, with exposure to AI hardware IMC and edge computing

Qualifications

• 10+ years of experience in SRAM/ROM memory development.
• Expertise in memory architecture, bitcell and peripheral circuit design.
• Experience with memory compilers and advanced CMOS technologies.
• Proven track record of silicon delivery and technical leadership.

Responsibilities

• Define and drive next-generation SRAM and ROM architectures for embedded and standalone memory products.
• Own memory roadmap development, architectural trade-off analysis, and technology strategy across multiple product lines.
• Lead optimization of performance, power, area (PPA), yield, and reliability targets.
• Architect memory arrays, peripheral circuits, redundancy schemes, ECC, power-management features, and test methodologies.
• Collaborate with circuit design, layout, verification, product, and process technology teams from concept through silicon validation and production.
• Drive innovations in low-voltage operation, high-speed access, low-power techniques, and memory reliability.

Skills

Memory architecture

CMOS memory design

Technical leadership

AI hardware IMC

Silicon validation

Education

B.E./B.Tech. in Electrical/ECE

M.Tech./M.S. in VLSI or related

Ph.D. in VLSI/Memory Design

Tools

Cadence

Synopsys

HSPICE

Job description

Job Responsibilities:

• Define and drive next-generation SRAM and ROM architectures for embedded and standalone memory products.
• Own memory roadmap development, architectural trade-off analysis, and technology strategy across multiple product lines.
• Lead optimization of performance, power, area (PPA), yield, and reliability targets.
• Architect memory arrays, peripheral circuits, redundancy schemes, ECC, power-management features, and test methodologies.
• Collaborate with circuit design, layout, verification, product, and process technology teams from concept through silicon validation and production.
• Drive innovation in low-voltage operation, high-speed access, low-power techniques, and memory reliability .
• Develop architectural models for memory performance, power consumption, area, and yield prediction.
• Lead root-cause analysis of silicon issues and define architectural improvements for future generations.
• Mentor engineers and provide technical leadership across cross-functional teams.
• Influence long-term memory technology roadmaps and IP strategy.

Special Plus - In-Memory Computing (IMC)

• Architect SRAM/ROM-based In-Memory Computing (IMC) solutions for AI/ML acceleration and edge-computing applications.
• Evaluate and develop digital, analog, and mixed-signal IMC architectures.
• Define compute-enabled memory macros supporting Vector-Matrix Multiplication (VMM) and Multiply-Accumulate (MAC) operations.
• Optimize energy efficiency, throughput, accuracy, and scalability for memory-centric AI workloads.
• Drive innovations involving ADC/DAC integration, quantization, calibration, and variation-tolerant compute architectures.
• Collaborate with AI accelerator, system architecture, and algorithm teams to enable next-generation intelligent computing solutions.

Education

• Bachelor's Degree (B.E./B.Tech.) in Electrical Engineering, Electronics Engineering, Electronics & Communication Engineering, or a closely related discipline.
• Master's Degree (M.Tech./M.S.) in VLSI Design, Microelectronics, Semiconductor Technology, Integrated Circuit Design, or related specialization preferred.
• Ph.D. in VLSI, Memory Design, Computer Engineering, or related field is a plus.

Experience & Skills

• 10+ years of experience in SRAM, ROM, embedded memory, custom memory, or memory compiler development.
• Deep expertise in memory architecture, bitcell and peripheral circuit design, redundancy, ECC, memory compilers, and advanced CMOS technologies.
• Strong understanding of memory characterization, silicon validation, reliability, and yield optimization.
• Proven track record of technical leadership, innovation, patent generation, and successful silicon delivery.
• Experience in AI hardware, In-Memory Computing (IMC), or memory-centric computing architectures is highly desirable.

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