Director of Research Development

WhiteSlips Job Management Consultants; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Benefits offered by this job

Health benefits

Total rewards package

Job summary

WhiteSlips Job Management Consultants seeks a senior leader to guide memory design for SRAM, ROM, and TCAM across advanced nodes. You will own end-to-end memory design flow, from bit cells to models, and mentor a cross‑site team responsible for delivering robust memory IP for AI, automotive, and HPC customers.

The role demands 20+ years in embedded memory, deep transistor‑level design knowledge, and strong scripting skills to automate design flows.

Qualifications

• BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering from a recognized university.
• 20+ years of hands-on embedded memory design experience including SRAM, Register File, TCAM, ROM architectures.
• Deep expertise across full memory design flow: architecture, schematic, layout planning, timing, model generation.

Responsibilities

• Lead a team of memory design engineers and own the full memory design flow from analysis to model generation.
• Deliver embedded memory IP powering AI, automotive, mobile and HPC, meeting area and power targets.
• Drive low-power, area-efficient embedded memory design and supervise layout activities with CAD teams.
• Manage project timelines across multiple concurrent projects and resolve technical and scheduling issues.
• Mentor engineers and foster collaboration across multi-site teams to ensure on-time delivery.

Skills

Memory design

Team leadership

Memory compiler

Verilog/VHDL

Design automation (Perl/Python)

Education

BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering

Tools

Perl

Python

Job description

• Lead a team of memory design engineers developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations for advanced process nodes
• Own the full memory design flow from bit cell analysis and architecture through schematic entry, simulation, layout planning, characterization, verification, and model generation
• Drive low-power, area-efficient embedded memory circuit design and supervise layout activities, interfacing directly with CAD teams on verification and compiler automation
• Manage project timelines, prioritize tasks across multiple concurrent projects, and resolve technical and scheduling issues proactively to ensure on-time delivery
• Build and maintain relationships with cross-functional teams including characterization, verification, and customer-facing engineering to align on deliverables and resolve escalations
• Apply and expand expertise in memory compiler development, transistor-level circuit design, and variation-aware design techniques for deep submicron technologies
• Mentor engineers, facilitate technical problem-solving, and foster collaboration across multi-site teams

The Impact You Will Have

• Deliver embedded memory IP that powers leading-edge semiconductor products across AI, automotive, mobile, and high-performance computing markets
• Enable Synopsys customers to meet aggressive area, power, and performance targets by providing robust, scalable memory solutions that work in silicon
• Reduce time-to-market for memory compiler releases by streamlining design flows, improving automation, and catching issues earlier in the development cycle
• Strengthen Company reputation as a trusted memory IP partner by resolving customer escalations quickly and delivering high-quality timing and power models
• Build a high-performing team culture where engineers grow technically, take ownership, and consistently deliver complex projects on schedule
• Drive process improvements that increase team productivity, reduce characterization cycles, and improve compiler quality metrics
• Shape the technical direction of embedded memory IP development at Company by contributing expertise in advanced node challenges and circuit innovation

What You'll Need

• BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering from a recognized university
• 20+ years of hands-on experience in embedded memory design including SRAM, Register File, TCAM, and ROM architecture and circuit implementation
• Deep expertise across the full memory design flow: architecture, schematic design, layout planning, characterization, timing analysis, and model generation
• Proven experience leading and managing engineering teams, delivering complex projects on schedule, and resolving technical and project issues across multiple priorities
• Strong proficiency in transistor-level circuit design for deep submicron and FinFET technologies, including variation-aware design techniques
• Mastery of Perl and Python for design automation and scripting
• Experience with memory compiler development and automation is a strong plus

Who You Are

• You can walk into a schematic review, spot a leakage path or timing violation in minutes, and explain the fix in a way that helps the engineer learn, not just comply
• When a project is slipping, you do not wait for the weekly status meeting, you pull the team together, identify the real blocker, and adjust the plan that day
• You know how to say no to a customer request that will derail the schedule without burning the relationship, and you can explain the tradeoff in terms they actually care about
• Debugging a characterization mismatch across process corners does not frustrate you, it engages you, because you know the answer is in the data and you will find it
• You build trust by doing what you say you will do, owning mistakes when they happen, and giving your team credit when things go right
• You are comfortable working across time zones and geographies, and you adapt your communication style to make sure nothing gets lost in translation

The Team You'll Be Part Of

You will lead a team within the Embedded Memory and Logic group, part of the Solutions Group. This team is responsible for developing standard and custom embedded SRAMs, ROMs, and TCAMs, delivering both functional and physical memory views through advanced memory compilers. The team covers the full spectrum of memory IP development, from bit cell analysis and architecture design to characterization, verification, and model generation. Your team will work closely with CAD, verification, and customer-facing engineering teams across Company global sites to deliver memory IP that enables the design of complex integrated circuits for leading-edge semiconductor products.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.