Sr Principal Design Engineer

Cadence Design Systems, Inc.; Ahmedabad District; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Cadence Design Systems, Inc. in Ahmedabad is hiring an RTL Design Engineer to develop and maintain the DDR Memory Controller IP. You will work on RTL design, feature enhancements, and verification across diverse configurations to ensure robust performance.

Responsibilities include verifying RTL, enabling lint and CDC cleanups, and supporting customer deployments. Strong Verilog/SystemVerilog with UVM experience is required, with DDR4/LPDDR4 knowledge highly valued.

Qualifications

• BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
• RTL Design using Verilog is a must.
• System Verilog experience and experience with UVM based environment usage / debugging is required.

Responsibilities

• Design and support the RTL of the DDR Memory Controller solution.
• Add new features into RTL and verify against various customer configurations.
• Support customers and ensure RTL is clean for LINT and CDC guidelines.

Skills

RTL Design

Verilog

SystemVerilog

UVM

AXI3/4

DDR Memory Controller

Education

BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI

Tools

LINT

CDC

Job description

BANGALORE

PUNE

NOIDA

AHMEDABAD

Full time

R45339

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

• RTL Design Engineer for DDR Memory Controller IP development team.

• The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.

• The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

Position Requirements:

• BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.

• RTL Design using Verilog is a must.

• System Verilog experience and experience with UVM based environment usage / debugging is required.

• AXI3/4 experience is desired.

• DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.

• Prior experience in IP development teams would be an added advantage.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.