Principal Design Engineer

Cadence Design Systems; Pune District; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

Cadence Design Systems in Pune is seeking a Performance Modeling Engineer to develop cycle-level models for next-generation DDR memory controller architectures and to enable data-driven design decisions.

You will correlate models with RTL configurations, work with memory architects, and analyze throughput versus hardware costs across scenarios, while building synthetic traffic and automation scripts for RTL simulations.

Qualifications

• BE/B.Tech/ME/M.Tech in ECE/EC/CS or similar with 8+ years of hardware modelling experience.
• Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM).
• Basic understanding of performance principles, queuing theory, throughput vs latency tradeoffs.

Responsibilities

• Develop cycle-level performance models in SystemC or C++.
• Correlate models to RTL configurations and traffic conditions.
• Collaborate with Memory Architects to understand feature requirements and implement them in the model.
• Analyze architectural trade-offs across scenarios and choices.
• Develop synthetic memory traffic/traces representative of real-world apps.
• Create scripts to automate generation of performance metrics post RTL simulation.

Skills

Performance modeling

C++ coding

SystemC

Education

BE/B.Tech or ME/M.Tech in ECE/EC/CS

Tools

SystemC

C++

TLM

Python

Verilog

UVM

Job description

Performance Modeling Engineer Location – India (Pune)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Summary We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

Responsibilities

• Develop cycle-level performance models in SystemC or C++
• Correlate performance models to match RTL configurations and traffic conditions
• Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
• Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
• Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
• Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

• BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar 8+ years of experience in hardware modeling, functional or performance
• Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
• Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Skills

• Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
• Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
• Experience using performance simulators – Memory Controller, NoC, CPU models
• Coding in Python and familiarity with packages like Pandas, Matplotlib
• Experience working with performance benchmarks – SPEC, STREAM, etc
• Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.