Sr PD Engineer

Tecquire Solutions Pvt. Ltd.; Dadri, Bengaluru; Remote; INR 1,800,000 - 3,000,000; Full time

Job summary

Tecquire Solutions Pvt. Ltd. in India is seeking a senior Physical Design engineer with 6+ years of experience to own end-to-end block PD, floorplanning, routing sign-off, and timing closure across MMMC scenarios.

You will perform STA (setup/hold, SI, OCV/derates), develop timing constraints (SDC), debug complex timing issues, and collaborate with STA/Sign-off teams to ensure clean sign-off; experience on 16nm/7nm/5nm is preferred; remote options are available.

Qualifications

• 6+ years of experience in physical design (PD)
• Strong STA experience with timing closure and sign-off
• Proficient in PD flow: floorplanning, CTS routing, sign-off

Responsibilities

• Own end-to-end physical design of assigned blocks (floorplan, route, sign-off).
• Drive timing closure across MMMC scenarios with deep analysis and debugging.
• Perform detailed STA (setup/hold, SI, OCV/derates) and ensure sign-off quality.
• Develop and validate timing constraints (SDC) with high coverage and accuracy.
• Collaborate with STA/Sign-off teams to ensure correlation and closure.
• Identify and resolve critical timing bottlenecks, congestion, and SI issues.
• Execute ECOs for timing, power, and area convergence.
• Perform physical verification (DRC/LVS/Antenna) and ensure clean sign-off.
• Analyze IR/EM and support PDN optimization.
• Contribute to flow improvements and automation.

Skills

Timing closure

Debugging timing issues

Scripting (Tcl/Python/Perl)

PD knowledge

Tools

Innovus

ICC2

Fusion Compiler

PrimeTime

Tempus

Job description

Experience: 6+ Years | Location: Noida / Bangalore / Remote

Own block-level physical design implementation with a strong focus on timing closure, driving convergence across PPA and sign-off.

Key Responsibilities

• Own end-to-end physical design of assigned blocks (floorplan route sign-off)
• Drive timing closure across MMMC scenarios with deep analysis and debugging
• Perform detailed STA (setup/hold, SI, OCV/derates) and ensure sign-off quality
• Develop and validate timing constraints (SDC) with high coverage and accuracy
• Work closely with STA/Sign-off teams to ensure correlation and closure
• Identify and resolve critical timing bottlenecks, congestion, and SI issue
• Execute ECOs for timing, power, and area convergence
• Perform physical verification (DRC/LVS/Antenna) and ensure clean sign-off
• Analyze IR/EM and support PDN optimization
• Contribute to flow improvements and automation

Skills Required

• Strong hands-on experience in PD tools (Innovus / ICC2 / Fusion Compiler)
• Strong STA expertise using PrimeTime / Tempus (must-have)
• Deep understanding of:
• Timing closure techniques (setup/hold fixing strategies)
• MMMC analysis and corner/mode interactions
• OCV/AOCV/POCV, SI/crosstalk effects
• Constraint development and validation (SDC)
• Ability to debug complex timing issues beyond tool reports
• Solid understanding of full PD flow (floorplan CTS routing sign-off)
• Strong scripting skills (Tcl required; Python/Perl preferred)

Preferred

• Experience at advanced nodes (16nm / 7nm / 5nm)
• Experience handling high-frequency or timing-critical blocks

Soft Skills

• Ability to independently own and close blocks under tight timelines

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.