Engineer/ Sr Memory Layout Engineer-DPG-LPDDR

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

1840 Micron Tech. OP India LLP is seeking a Senior Memory Layout Engineer in Hyderabad, India. In this role, you will work on innovative memory solutions, driving high-quality layout implementations and collaborating with a dedicated team.

The ideal candidate should have over 6 years of experience in memory and full-custom layout development, significant knowledge in DRAM/LPDDR architecture, and expertise in tools like Cadence Virtuoso and Calibre.

Qualifications

• 6+ years of proven experience in memory and full-custom layout development.
• Strong understanding of DRAM/LPDDR memory architecture.
• Ability to independently plan and execute layout blocks.

Responsibilities

• Hands-on experience on Bit cell layout creation and pitch matching.
• Strong exposure to Row decoder (XDEC) and column decoder (YDEC) layout development.
• Leverage AI/ML knowledge for data-driven optimization and layout automation.

Skills

Bit cell layout creation

Row decoder layout development

Memory architecture understanding

Cadence Virtuoso

Calibre DRC/LVS

Transistor matching strategies

AI/ML knowledge

Education

B.Tech/B.E in Electronics, Electronics&Communications, or VLSI Engineering

M.Tech in Electronics engineering, Microelectronics or VLSI Engineering

Job description

Senior Memory Layout Engineer - DPG‑LPDDR

At Micron, you will work on innovative memory and storage solutions, helping transform data into intelligence quickly. You will join a dedicated team collaborating to develop world‑class products that set industry standards.

Responsibilities and Qualifications

• Hands‑on experience on Bit cell layout creation and pitch matching
• Strong exposure on Row decoder (XDEC) and column decoder (YDEC) layout development
• 6+ years of proven experience in memory and full‑custom layout development
• Memory array hierarchy and decode path understanding
• Proficient with Cadence Virtuoso for custom layout implementation
• Solid experience with Calibre DRC/LVS including debug and closure
• Strong understanding of DRAM/LPDDR memory architecture, array organization, and peripheral integration
• Apply strong device physics expertise to drive high‑quality layout implementation, including transistor matching strategies, well and substrate engineering, parasitic optimization, and EM/ESD reliability considerations
• Ability to independently plan, execute and deliver layout blocks with minimal supervision
• Strong ownership mindset with focus on quality, power and schedule
• Leverage AI/ML knowledge as a value‑add to support data‑driven optimization, layout automation initiatives, and improved debug and correlation workflows

Education

• B.Tech/B.E in Electronics, Electronics&Communications, or VLSI Engineering
• M.Tech in Electronics engineering, Microelectronics or VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]. Micron prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.