Sr. Memory Layout Design Engineer

Broadcom Inc.; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Broadcom Inc. in Bengaluru is seeking an experienced Memory Layout Engineer to design and verify memory layout stacks for advanced CMOS processes.

You will apply layout guidelines, manage floor-planning, and deliver end-to-end layouts on schedule while coordinating with SOC and library teams. The role requires at least 5 years of memory layout experience, a Bachelor's degree, and proficiency with Cadence tools (Virtuoso XL/VXL/EXL) and CALIBRE.

Qualifications

• Bachelor's degree required.
• 5+ years in memory layout design and physical verification.
• Proficiency with Cadence tools and CALIBRE verification tools.
• Strong memory layout experience in CMOS processes.
• Digital layout experience; analog layout is a plus.

Responsibilities

• Apply layout guidelines, new process rules and technical requirements.
• Manage scheduling, timelines and layout floor-planning.
• Deliver start-to-end layout with quality on schedule.
• Communicate with SOC/library teams and adapt to new methodologies.

Skills

Memory layout

Physical verification

Floor planning

Chip integration

Memory architecture

Scripting (SKILL)

Automation in layout

Project leadership

Education

Bachelor's degree

Tools

Cadence Virtuoso XL

Cadence VXL/EXL

CALIBRE verification tools

Job description

Job Requirements

• Minimum 5 years of experience with strong layout knowledge
• Bachelor's degree required.
• Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Responsible for start to end deliverables with quality within the planned schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

Skill Set (Memory)

• Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
• Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
• Proficiency in floor-planning, hierarchy layout, and chip integration.
• Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines
• Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.
• Ability to lead, train junior engineers, and manage projects effectively.
• Good knowledge of memory layout topology; experience with memory compilers is a plus.
• Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
• Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

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