Sr. Lead Physical Design - Power/IR/EM Engineering

L&T Semiconductor Technologies; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

L&T Semiconductor Technologies in Bengaluru seeks a senior engineer to lead full chip level Power Distribution Network design, focusing on peak current requirements and IR drop assessment at the SoC level. The role involves coordinating with system, PMIC and silicon package teams to ensure robust voltage response and reliable power delivery.

Candidates should have strong scripting and data analysis skills, be adept with EDA tools, and thrive in a dynamic team environment.

Qualifications

• Experience in EMIR signoff flow at SOC level.
• Strong IR drop analysis (dynamic & static) for power grids.
• Ability to model on-die PDN and IP current profiles.
• Proficiency in scripting and data analysis.
• Collaboration with system, PMIC, and silicon teams.

Responsibilities

• Develop and run EMIR signoff flow at SOC.
• Close EMIR based on dynamic and static IR.
• Provide feedback on grid robustness to floorplan team.
• Model voltage response of the power delivery network with PMIC and silicon package teams.
• Model PDN including on-die power gating and inrush currents.
• Model current profiles and peak currents of IPs.
• Strong problem solving, scripting, data analysis; experience with EDA tools.
• Teamwork and adaptability in a dynamic environment.

Skills

EMIR Signoff

IR Drop Analysis

Power Grid Modeling

Scripting

Data Analysis

EDA Tools

Teamwork

SoC PDN

Education

Bachelors/Masters in EE/EC/CS

Tools

EDA Tools

Job description

This position is for senior level engineer Full chip level Power Distribution Network Design. He Shall be leading instrumental in power grid planning on SoC level for peak current requirements & to have Dynamic & Static IR drop assessment & closure.

Key Responsiblities

• Ability to Develop & run EMIR Signoff flow at SOC
• Ability to Close EMIR based on Dynamic (vectored and vectorless) & Static IR
• Can provide Feedback on Grid Robustness to SOC floorplan team
• Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.
• Model of the power delivery networks, including on-die power gating and in-rush current profiles.
• Model of the current profiles and peak current demands of various IPs.
• Strong Skills in problem solving, scripting, data analysis and experience with EDA tools.
• Teamwork / flexibility / ability to thrive in a dynamic environment are very important

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering