EMIR Engineer

Modernize Chip Solutions (MCS); Bengaluru; On-site; INR 1,400,000 - 2,800,000; Full time

Job summary

Modernize Chip Solutions (MCS) in Bengaluru is seeking a power integrity specialist to drive low-power SoC validation and UPF-based integration for advanced node designs. You will collaborate with the PMIC and silicon package team to model and optimize the power delivery network, including on-die power gating and peak current demands for multiple IPs.

The role emphasizes cross-functional coordination and precise PDN modelling to ensure robust power integrity across the SOC, with a focus on

Qualifications

• Strong expertise in low-power and ultra-low-power SoC implementation to lead power-intent validation and integration using UPF methodologies for ADI's advanced node designs.
• Ability to collaborate and resolve dynamic & static IR issues.
• Good exposure to high-frequency design convergence for PDN and descent exposure VCD flows, RHVoltus/Voltus, and Vmin flows.
• Evaluate and optimise different power distributions (voltage rail assignments, regulator assignment) for a SoC.
• Modelling the power delivery networks, including on-die power gating and in-rush current profiles.
• Modelling the current profiles and peak current demands of various IPs.
• Evaluate and optimise voltage rail assignment and regulator requirements for SOC.
• Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.

Responsibilities

• Lead power-intent validation and integration using UPF methodologies.
• Collaborate with system, PMIC and silicon package teams to model voltage responses.
• Model and optimise PDN, on-die power gating, and current profiles for IPs.
• Assess voltage rail and regulator requirements for SOC performance.

Job description

• Strong expertise in low-power and ultra-low-power SoC implementation to lead power-intent validation and integration using UPF methodologies for ADI's advanced node designs.
• Ability to collaborate and resolve dynamic & static IR issues.
• Good exposure to high-frequency design convergence for PDN and descent exposure VCD flows, RHVoltus/Voltus, and Vmin flows.
• Evaluate and optimise different power distributions (voltage rail assignments, regulator assignment) for a SoC.
• Modelling the power delivery networks, including on-die power gating and in-rush current profiles.
• Modelling the current profiles and peak current demands of various IPs.
• Evaluate and optimise voltage rail assignment and regulator requirements for SOC.
• Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.