Lead ASIC PD / EMIR Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,500,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru is seeking a seasoned Lead ASIC PD / EMIR Engineer to own SoC-level IR Drop, EM, and Power EM sign-off for advanced digital ASIC designs.

You will drive EMIR closure by identifying root causes of power integrity and electromigration issues, collaborate with the PD team to ensure timely sign-off, and deliver robust power integrity improvements across complex chips.

Qualifications

• 8+ years of VLSI/Physical Design experience.
• 3+ years hands-on PDN and EMIR closure for digital ASICs.
• Strong EMIR analysis and sign-off methodologies.

Responsibilities

• Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
• Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
• Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
• Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
• Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.

Skills

VLSI/Physical Design

PDN and EMIR closure

EMIR analysis

Debugging and analytics

Cross-functional collaboration

Job description

We're Hiring | Lead ASIC PD / EMIR Engineer

Are you passionate about power integrity and sign-off for advanced digital SoCs? We're looking for an experienced PDN / EMIR Engineer to join our growing VLSI team.

Required Experience

• 8+ years of overall VLSI/Physical Design experience is preferred.
• 3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
• Strong expertise with industry-standard EMIR analysis and sign-off methodologies.
• Excellent debugging, analytical, and cross-functional collaboration skills.

Key Responsibilities

• Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
• Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
• Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
• Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
• Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.