Sr. Lead ASIC design Engineer - Digital Design

NXP Semiconductors; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading semiconductor company in Hyderabad seeks an experienced engineer to define and implement hardware architectures optimized for AI inference SoCs. The role requires over 7 years of ASIC/SoC RTL design experience and strong collaboration with various design teams. Ideal candidates should have a solid grasp of synthesis, timing, and power analysis, along with debugging skills. This position offers a chance to work on cutting-edge technology in a dynamic environment.

Qualifications

• 7+ years of experience in ASIC/SoC RTL design.
• Solid understanding of synthesis, timing, and power analysis.
• Experience with Lint/CDC/RDC flows.
• Strong debugging and root-cause analysis capability.

Responsibilities

• Define and implement hardware architectures optimized for AI inference SOC's.
• Contribute to micro-architecture definition and evaluate design trade-offs.
• Collaborate with physical design teams on synthesis, timing closure, and power optimization.
• Ensure design correctness with verification team inclusion.
• Analyze performance bottlenecks and validate AI inference use cases.

Skills

ASIC/SoC RTL design

Synthesis understanding

Timing analysis

Power analysis

Debugging skills

Root-cause analysis

Job description

Responsibilities

• Define and implement hardware architectures optimized for AI inference SOC's
• Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO's
• Collaborate with physical design teams on synthesis, timing closure, and power optimization.
• Collaborate with verification team to ensure design correctness.
• Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.

Required Qualifications

• 7+ years of experience in ASIC/SoC RTL design
• Solid understanding of synthesis, timing, and power analysis
• Experience with Lint/CDC/RDC flows
• Strong debugging and root-cause analysis capability