AI Accelerator Chip Architect

Capgemini Engineering; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Capgemini Engineering in Bengaluru is seeking a senior ASIC/SoC architect to lead architecture and technical strategy for AI/ML acceleration silicon, including compute engines, memory hierarchy, interconnects, and software enablement. The role requires 15+ years in ASIC/SoC design, strong AI workloads know-how, and experience in compute sub-systems such as ARM Neoverse or RISC-V, plus NoC concepts.

You will collaborate with RTL and verification teams and engage with customers to define solutions

Qualifications

• 15+ years in ASIC/SoC design.
• Deep experience in AI workloads and inference pipelines.
• Strong background in compute architecture and memory systems.
• Experience in RTL design and verification.
• Customer-facing engagement and solution definition.

Responsibilities

• Define AI accelerator architecture; analyze AI workloads and mapping strategies.
• Drive NPU/Matrix Engine/MAC architecture decisions.
• Define memory hierarchy and bandwidth requirements.
• Guide RTL and verification teams.
• Support customer workshops and define solutions.
• Drive accelerator roadmap and differentiation.

Skills

ASIC/SoC design

AI workloads & inference pipelines

Compute architecture

Memory systems

RTL design & verification

Customer-facing capability

NoC concepts (Arteris/ ARM)

Job description

Roles & Responsibilities

Lead architecture and technical strategy for AI/ML acceleration silicon, including compute engines, memory architecture, interconnects, and software enablement.

Roles & Responsibilities

Lead architecture and technical strategy for AI/ML acceleration silicon, including compute engines, memory architecture, interconnects, and software enablement.

Key Responsibilities

• Define AI accelerator architecture.Analyze AI workloads and mapping strategies.
• Drive NPU/Matrix Engine/MAC architecture decisions.
• Define memory hierarchy and bandwidth requirements.
• Guide RTL and verification teams.
• Support customer technical workshops and solution definition.
• Drive accelerator roadmap and differentiation.

Our Ideal Candidate

• 15+ years in ASIC/SoC design.
• Prior experience on AI, GPU, DSP, NPU, TPU, or HPC silicon.
• Strong understanding of AI workloads and inference pipelines.
• Experience in compute architecture and memory systems e.g. ARM Neoverse, RISC-V mesh based compute sub-system
• Compute Sub-system experience
• Complex NoC experience e.g. Arteris / ARM
• Understanding on other processor such as ARM A, M and R series
• Understanding of RTL design and verification.
• Performance modeling experience and assessment using virtual or emulation platform.
• Strong customer-facing capability.