Formal Verification Engineer

Intel Corporation; Bengaluru; Sur place; INR 2 500 000 - 4 200 000; Plein temps

Résumé du poste

Intel Corporation in Bengaluru, India seeks an experienced Formal Verification Engineer for the Silicon Chassis team. You will own end-to-end formal verification across interconnect fabric and protocol bridges, collaborating with architecture, design and software teams.

The role requires strong formal depth and expertise in SystemVerilog/Verilog, model checking, and abstraction modeling. AI-assisted workflows are part of the daily development environment, with emphasis on rigorous verification

Qualifications

• BS/MS in Electrical Engineering, Computer Science, or related field, with 5+ years of relevant experience in formal verification.
• Proficiency in formal verification tools and methodologies, including model checking and equivalence checking.
• Strong knowledge of System Verilog, Verilog, and logic/microarchitecture fundamentals.
• Experience with abstraction modeling, simulation techniques, and convergence strategies.
• Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG).

Responsabilités

• Develop and execute formal verification test and coverage plans, including scope, strategy, and techniques.
• Create abstraction models to enable convergence on designs and apply abstraction techniques to formal verification.
• Generate and validate formal proofs to implement verification plans and resolve failing tests through corrective measures.
• Collaborate across architecture, RTL design, and physical design teams to improve verification of complex features.
• Maintain and enhance existing formal verification infrastructure, tools, and methodologies.
• Simplify and model problems using architecture modeling techniques to verify protocols and architectures.
• Utilize tools to formally prove design protocols, resolve BDD complexity, and optimize data paths.
• Document test plans, track verification progress, and drive technical reviews with cross-functional teams.

Connaissances

Formal verification

SystemVerilog

Verilog

Model checking

Equivalence checking

Formation

BS/MS in Electrical Engineering or Computer Science

Outils

BDD

Description du poste

Job Details: Job Description: The Role and Impact Intel is seeking a Formal Verification Engineer for the Silicon Chassis team.

The role focuses on applying formal methods to exhaustively verify our interconnect fabric, protocol bridges, and link-layer logic. You will own end-to-end formal verification, from property specification through proof convergence - across multiple protocol domains. You will work closely with architecture, design, and software teams and are expected to contribute across traditional discipline boundaries. This role requires strong Formal depth, solid protocol knowledge, hands-on coding strength, and growing ability to mentor junior engineers. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.

Key Responsibilities

• Develop and execute comprehensive formal verification test and coverage plans, including the definition of scope, strategy, and techniques.
• Create abstraction models to enable convergence on designs and apply abstraction techniques to formal verification.
• Generate and validate formal proofs to implement verification plans and resolve failing tests through corrective measures.
• Collaborate across architecture, RTL design, and physical design teams to improve the verification of complex architectural and microarchitectural features.
• Maintain and enhance existing formal verification infrastructure, tools, and methodologies.
• Simplify and model problems using architecture modeling techniques to verify protocols and architectures.
• Utilize tools to formally prove design protocols, resolve BDD complexity, and optimize data paths.
• Document test plans, track verification progress, and drive technical reviews with cross-functional teams.

Minimum Qualifications

• BS/MS in Electrical Engineering, Computer Science, or related field, with 5+ years of relevant experience in formal verification.
• Proficiency in formal verification tools and methodologies, including model checking and equivalence checking.
• Strong knowledge of System Verilog, Verilog, and logic/microarchitecture fundamentals.
• Experience with abstraction modeling, simulation techniques, and convergence strategies.
• Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG).

Preferred Qualifications

• Proven ability to apply problem-solving skills to resolve complex architectural and verification challenges.
• Strong collaboration and teamwork skills, with experience working in cross-functional teams.
• Excellent technical documentation and communication abilities.
• Passion for driving innovation and advancing the state of verification tools and methodologies.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Job posting details (such as work model, location or time type) are subject to change.

Position of Trust N/A

Work Model for this Role This role will require an on-site presence.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.