SoC/IP Architect

Texas Instruments; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

Texas Instruments is seeking a SoC/IP Architect to work on high-speed mixed-signal communication circuits. Responsibilities include defining SoC architecture, optimizing designs, and conducting performance analyses.

The ideal candidate has 8+ years of experience in SoC architecture and chip development, with a proven track record in successful chip tape-outs and so on. The role offers an opportunity to collaborate with a talented team to drive architectural decisions and ensure successful implementations.

Qualifications

• 8+ years of experience in SoC architecture, IP design, or chip development.
• Proven track record of successful chip tape‑outs and silicon bring‑up.
• Hands-on experience with SoC integration and managing complex multi‑IP designs.

Responsibilities

• Define and document SoC architecture including system topology and IP selection.
• Establish Performance, Power, and Area (PPA) targets and drive architectural decisions.
• Design and optimize interconnect architectures including bus structures.
• Create architectural models and simulations to validate design decisions early.

Skills

SoC architecture

IP design

Chip development

Performance, Power, Area (PPA) management

Hardware-software partitioning

Security-aware architecture design

Job description

In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the-art process technology, as well as design high-performance digital circuits interfacing to leading-edge analog circuitry as part of an overall system.

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging of high-speed communication chips at both the circuit level and behavioral level. You will prepare test methods and specifications, assist in preparation of application information, data sheets, and demo boards, develop solutions to complex problems, plan and organize work for multiple independent tasks, and communicate with a talented team of analog and digital design engineers to solve problems and present information.

Role: SoC/IP Architect

Key Responsibilities

• Define and document SoC architecture including system topology, IP selection, and integration strategy for mixed-signal MCUs.
• Establish Performance, Power, and Area (PPA) targets and drive architectural decisions to meet these goals.
• Design and optimize interconnect architectures including bus structures.
• Perform hardware-software partitioning to optimize functionality across hardware accelerators and software implementations.
• Create architectural models and simulations to validate design decisions early in the development cycle.
• Design, customize, or select IP blocks such as processors, memory controllers, DSPs, accelerators, and peripherals.
• Ensure IP blocks are reusable, configurable, and scalable across multiple product variants.
• Select and integrate third-party and internal IP cores.
• Define IP specifications and collaborate with IP design teams to ensure requirements are met.
• Analyze and optimize data flow and memory hierarchy to eliminate bottlenecks and maximize system throughput.
• Implement power management strategies and multi‑domain power architecture.
• Design security‑aware architectures with hardware-based security features, secure boot, and isolation mechanisms.
• Conduct performance analysis and trade‑off studies to balance competing requirements.
• Evaluate emerging technologies and methodologies for future product roadmaps.
• Work closely with RTL design, verification, physical design, and software teams to ensure architectural feasibility and successful implementation.
• Support early software bring‑up by providing architectural documentation and working models.
• Collaborate with system engineers and customers to understand application requirements and translate them into technical specifications.
• Participate in design reviews and provide technical guidance to engineering teams.
• Interface with validation teams to develop comprehensive test strategies and ensure design quality.

Experience

• 8+ years of experience in SoC architecture, IP design, or chip development.
• Proven track record of successful chip tape‑outs and silicon bring‑up.
• Hands‑on experience with SoC integration and managing complex multi‑IP designs.
• Experience defining and meeting PPA (Performance, Power, Area) targets for production chips.

Requirements

• ECL/GTC Required: Yes

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.