SOC Design Verification Engineer

Samsung Electronics America; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) in Bengaluru seeks an experienced SOC verification engineer to drive verification of IPs and blocks from test plan development to GLS sign-off, collaborating with PD, RTL and DFT teams.

The role requires 4–7 years in sub-system/SOC verification, strong SystemVerilog/UVM/OVM skills, test bench creation, and knowledge of AMBA protocols; experience with high-speed interfaces is a plus. A relevant engineering degree is expected.

Qualifications

• 4–7 years in Sub-system/SOC verification.
• Experience in developing test benches from scratch using UVM components (BFM, agents, monitor, scoreboard, checkers) and third-party VIP integration.
• Proficient in SystemVerilog/UVM/OVM verification methodologies and scripting.

Responsibilities

• Execute DV test plans including creation/modification of test benches and integration of checkers/scoreboards.
• Debug complex failures and optimize simulations with cross-domain teams (PD, RTL, DFT).
• Ensure coverage is sign-off and regression runs with power-awareness and performance considerations.

Skills

SystemVerilog

UVM

OVM

Test bench development

Constrained random

AMBA AXI/AHB/APB

Scripting

SVA

Education

B.Tech/B.E./M.Tech

Job description

Position Summary About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting‑edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R\&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Role and Responsibilities

Will be involved in SOC verification and responsible for verifying one or more IP(s)/Block(s) from test plan development to GLS sign-off with code/functional coverage closure. He/she will work closely work with cross-domains team (PD, RTL, DFT) for reviews, debug and for technical discussions.

Required Skills

• 4~7 years working experience in Sub-system, SOC level verification (including GLS).
• Experience in developing test bench from scratch -- UVM components : BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration.
• Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements.
• Creates efficient test plans for RTL validation and Gate level simulations.
• Expertise in System Verilog, UVM, and/or OVM based verification methodologies.
• Experience in OOPs concepts, coverage driven constrained random validation.
• Must have very good knowledge on AMBA standards (AXI, AHB, APB).
• Looking for individual with Hands‑on experience in Memory protocols such as - HBM2/HBM3 OR LPDDR4~5x OR GDDRx is highly desirable.
• Any experience on high-speed protocols like - PCIe, Ethernet, High speed SerDes is a plus
• Working knowledge of scripting, SVA.

Execution of DV test plan which includes

• Creation/modification of the test bench.
• Implementation of software/programming sequence.
• Creation/integration of checkers and scoreboards from unit level UVM environment.
• Resolution of compile and simulation errors.
• Innovative optimizations to reduce simulation time.
• Complex failure debug: Isolating design related failure by systematically identifying and eliminating issues related to Test bench/programming sequence in close collaboration with unit verification engineers, logic designers and architects
• Coverage sign-off - Code (block, expression, fsm), toggle and functional coverage
• Continuous regressions (X-prop, Power-aware and performance runs ) and failure closure

Skills and Qualifications

Experience – 4 to 7 years Qualifications B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R\&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Samsung Electronics is a global leader in technology, opening new possibilities for people everywhere. Through relentless innovation and discovery, we are transforming the worlds of TVs, smartphones, wearable devices, tablets, digital appliances, and network systems, and the entire semiconductor industry with our memory, system LSI, foundry, and LED solutions. Samsung is also leading in the development of the Internet of Things through, among others, our Smart Home and Digital Health initiatives. Since being established in 1969, Samsung Electronics has grown into one of the world’s leading technology companies, and become recognized as one of the top global brands. Our network now extends across the world, and Samsung takes great pride in the creativity and diversity of its talented people, who drive our growth. To discover more, please visit our official newsroom at (https://news.samsung.com/global/).