SOC Design Verification Engineer

Samsung Electronics Perú; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading semiconductor company in Bengaluru is searching for a SOC Design Verification Engineer with 4-7 years of experience. This role involves verifying SOC IP blocks, developing comprehensive test plans, and collaborating with cross-domain teams. Proficiency in UVM, System Verilog, and AMBA standards is essential. Ideal candidates will also have hands-on experience with memory protocols and high-speed communication standards. The position offers an opportunity to work on cutting-edge technologies in an innovative environment.

Qualifications

• 4-7 years of working experience in SOC level verification including GLS.
• Proficient in creating test benches and pre-silicon functional verification tests.
• Hands-on experience with high-speed protocols like PCIe and Ethernet is a plus.

Responsibilities

• Verify SOC and IP blocks from test plan to GLS sign-off.
• Collaborate with cross-domain teams for reviews and technical discussions.
• Create and implement efficient test plans for RTL validation.

Skills

Sub-system verification

SOC level verification

UVM components

System Verilog

AMBA standards

Memory protocols

Scripting

Debugging skills

Education

B.Tech/B.E/M.Tech/M.E

Job description

SOC Design Verification Engineer page is loaded## SOC Design Verification Engineerlocations: SSIR, Goldstone, Bangalore, Indiaposted on: Posted Todaytime left to apply: End Date: March 27, 2027 (30+ days left to apply)job requisition id: R115109**Position Summary**About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.**Role and Responsibilities**Will be involved in SOC verification and responsible for verifying one or more IP(s)/Block(s) from test plan development to GLS sign-off with code/functional coverage closure. He/she will work closely work with cross-domains team (PD, RTL, DFT) for reviews, debug and for technical discussions.**Required Skills:**• 4~7 years working experience in Sub-system, SOC level verification (including GLS). • Experience in developing test bench from scratch -- UVM components : BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration. • Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements. • Creates efficient test plans for RTL validation and Gate level simulations. • Expertise in System Verilog, UVM, and/or OVM based verification methodologies. • Experience in OOPs concepts, coverage driven constrained random validation. • Must have very good knowledge on AMBA standards (AXI, AHB, APB). • Looking for individual with Hands-on experience in Memory protocols such as - HBM2/HBM3 OR LPDDR4~5x OR GDDRx is highly desirable. • Any experience on high-speed protocols like - PCIe, Ethernet, High speed SerDes is a plus • Working knowledge of scripting, SVA. • Execution of DV test plan which includes • Creation/modification of the test bench. • Implementation of software/programming sequence. • Creation/integration of checkers and scoreboards from unit level UVM environment. • Resolution of compile and simulation errors. • Innovative optimizations to reduce simulation time. • Complex failure debug: Isolating design related failure by systematically identifying and eliminating issues related to Test bench/programming sequence in close collaboration with unit verification engineers, logic designers and architects • Coverage sign-off - Code (block, expression, fsm), toggle and functional coverage • Continuous regressions (X-prop, Power-aware and performance runs ) and failure closure**Skills and Qualifications****Experience – 4 to 7 years****Qualifications*** B.Tech/B.E/M.Tech/M.E**Disclaimer**Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\* Please visit to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click .