Silicon Validation Director

Mulya Technologies; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

Competitive compensation

Equity participation

Flexible work arrangements

Comprehensive benefits

Job summary

Mulya Technologies is seeking a seasoned Silicon Validation Lead to drive end-to-end validation of next-generation SoC platforms integrating PCIe, CXL, DDR5, and Caliptra RoT. You will own silicon bring-up, define plans, and guide a cross-functional team across design, DV, firmware, and software to ensure first-pass quality.

You will lead validation strategies, develop test infrastructure, and coordinate with external IP vendors and labs.

Qualifications

• 18+ years of hands-on silicon or hardware validation experience.
• 6+ years in a Manager/Lead or staff-level role.
• Deep expertise in PCIe and CXL with strong measurement and debug skills.

Responsibilities

• Drive silicon bring-up from power-on to full functional validation and sign-off.
• Define test strategies, coverage matrices, and validation plans.
• Lead cross-functional teams across RTL, firmware, and software for hand-offs.
• Coordinate with IP vendors, OEM/ODM partners, and labs for interoperability.

Skills

PCIe Gen4/5/6

CXL

DDR5 memory

RISC-V cores

Memory Fabric

Debugging & silicon bring-up

Test automation & CI/CD

Lab instrumentation

Education

Bachelor's or Master's in Electrical/Computer Engineering or CS

Tools

JTAG / GDB

OpenOCD

Oscilloscopes / Protocol analyzers

Python / Tcl / Bash

Job description

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale

.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the futur

e.

bad

Department: Silicon Engineering / Hardware Valida

tionEmployment Type: Full-

Time

We are a semiconductor company pioneering high-performance interconnect and chip-tochip communication solut

ions.Our engineering teams push the boundaries of what is possible in silicon design, validation, and system integra

tion.We are looking for a seasoned Silicon Validation Lead to join our R&D organization and drive end-to-end validation of complex SoC platf

orms.

Role Ov

erview

As the Silicon Validation Director you will own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms that integrate PCIe, CXL, DDR5, RISC-V processors, Memory Fabric, PCIe Switch, and Caliptra Root of Trust (RoT) subs

ystems.

You will lead a cross-functional validation team, define test strategies, and act as the primary technical interface between design, architecture, firmware, and system teams to ensure first-pass silicon quality and robust production re

adiness.

Key Respons

ibilitiesSilicon Bring-Up & Validation Lead pre- and post-silicon validation for complex SoCs encompassing PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5 memory subsystems, RISC-V processor cores, Memory Fabric, PCIe Switch, and Caliptr

a RoT IP.

Drive silicon bring-up from power-on through full functional validation, characterization, and compliance testing. Develop and own comprehensive silicon validation plans, test coverage matrices, and sign-off criteria aligned with tapeout and production m

ilestones.

Execute and manage compliance and interoperability testing against PCIe, CXL, JEDEC DDR5, and relevant security/RoT standards. Test Architecture &am

Define test infrastructure architecture: board-level bring-up environments, FPGA prototypes, simulation correlation, and lab automation

frameworks.

Drive development of validation collateral including test plans, test suites, regression frameworks, and pass/fail criteria for all integrate

d subsystems.

Establish coverage tracking dashboards and triage processes to systematically reduce validation escapes. Debug & Root

Lead deep-dive debugging of complex multi-layer failures spanning RTL, firmware, hardware, and system software. Utilize protocol analyzers, logic analyzers, oscilloscopes, and CXL/PCIe test equipment (e.g., Teledyne LeCroy, Keysight, Spirent) to isolate and chara

cterize issues.

Author and maintain detailed bug reports, failure analysis documents, and errata for silicon revisions. Team Leadership &am

Lead and mentor a team of validation engineers; set technical direction, review deliverables, and foster a culture of e

Collaborate closely with RTL design, DV, firmware, and software teams to ensure seamless hand-off from pre-silicon simulation to physical s

Interface with external IP vendors, OEM/ODM partners, and compliance labs for interoperability and certif

ication activities.

Represent the validation team in architecture reviews, design reviews, and program planning meetings. Process & Co

Champion test automation and CI/CD integration for r

egression management.

Drive lessons-learned processes across silicon spins and contribute to validation met

Establish and maintain lab safety, equipment inventory, and test asset man

Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Sc

ience, or related field.

18+ years of hands-on silicon validation or hardware validation engineering experience, with at least 6 years in a Manager/

Lead or staff-level role.

Deep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer ch

aracterization, and debug.

Strong hands-on experience with CXL (1.1 / 2.0 / 3.0): memory semantic protocols, device types (Type 1/2/3), coherency mechanisms, an

d interoperability testing.

Extensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC c

ompliance, and RAS features.

Solid experience with RISC-V processor bring-up, ISA compliance validation, and core/cluster debug using JT

AG and hardware debug probes.

Hands-on experience with Memory Fabric architectures: bandwidth/latency characterization, coherency validati

on, and fabric stress testing.

Experience validating PCIe Switch silicon: multi-port topologies, QoS, hot-plug

, and error-handling scenarios. Experience with Caliptra Root of Trust or equivalent security subsystem validation: secure boot, firmware attestation, cryptographic engine verific

ation, and DICE/RoT compliance

.

Technical Skills Domain

SkillsProtocols

Gen 4/5/6,CXL

C-V (RV64GC, RISC-V Debug Spec),JTAG Security Caliptra RoT, Secure Boot, DICE, TPM concepts Intercon

nect Memory Fabric, PCIe Switch,

NoC fundamentals InstrumentationProtocol analyzers, BERT

, oscilloscopes, VNAs AutomationPython, Tcl, Bash, PyATS, Robot Framework EDA / Debug Sig

nal Tap, Chip

Scope, OpenOCD, GDB

What We Offer Opportunity to work on cutting-edge, industry-defining interconn

ect and semiconductor technology. Collaborative, high-trust engineering culture with direct access to architecture and design teams. Competitive compensation, equity participa

tion, and comprehensive benefits. Flexible work arrangements and a commitme

nt to continued technical growth.We

are an equal opportunity employer. We celebrate diversity and are committed to creating an inclusi

ve environment for all employees.

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we