Lead Chip Validation Engineer

HypTechie; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

HypTechie in Bengaluru is seeking a highly experienced Lead Chip Validation Engineer to drive validation across pre- and post-silicon phases for PCIe Gen5/6, high-speed analog/mixed-signal blocks, and system-level bring-up.

You will lead cross-functional teams, own the validation strategy, and mentor junior engineers while implementing automated testing with Perl/TCL/Shell and SystemVerilog/UVM environments. 8+ years of hands-on experience required.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering (BSEE/MSEE).
• 8+ years hands-on chip validation, silicon bring-up, and test development.
• Proven expertise in PCIe Gen5/6, Ethernet PHY (IEEE 802.3), and SERDES.
• Strong programming in C/C++, SystemVerilog, and Object-Oriented Programming.
• In-depth experience in firmware, driver, and microcontroller-based SoC debug.
• Familiarity with testbench development using UVM or equivalent environments.
• PERL, TCL, Shell scripting for automation and data analysis.
• Knowledge of PLL, CDR, AMS analog/digital validation a strong plus.

Responsibilities

• Plan and execute silicon validation strategies for next-generation semiconductor products.
• Develop detailed validation schedules, define test plans, and coordinate execution across teams.
• Lead validation of PCIe Gen5/6 interfaces, high-speed analog/mixed-signal blocks, and multi-clock domains.
• Perform hardware bring-up, debug hardware-software integration issues, and support board/system validation.
• Collaborate with hardware, firmware, and driver teams to isolate and root cause issues.
• Utilize scripting to automate testing and manage regression environments.
• Analyze compliance with PCIe/IEEE 802.3 Ethernet standards and ensure robustness.
• Contribute to SystemVerilog/UVM-based validation environments and reusable test components.
• Drive issue resolution and own validation deliverables; mentor junior engineers.

Skills

PCIe Gen5/Gen6 validation

C/C++

SystemVerilog

UVM testbenches

Perl/TCL/Shell

Firmware debugging

Verilog/VHDL debugging

Debug & bring-up

Leadership

Education

BSEE/MSEE

Tools

UVM

Git

Jenkins

Job description

We are seeking a highly experienced and results‑driven Lead Chip Validation Engineer to join our high-performance silicon engineering team. This role is ideal for professionals with strong hands‑on experience in PCIe Gen5/Gen6 validation, embedded firmware debug, and complex mixed‑signal hardware. The selected candidate will play a key role in ensuring first‑silicon success of cutting‑edge semiconductor designs. You will lead and execute silicon validation across pre‑ and post‑silicon phases, work closely with hardware, firmware, and software teams, and own the debug, bring‑up, and validation strategy for high‑performance chips.

Key Responsibilities:

• Plan and execute silicon validation strategies for next‑generation semiconductor products.
• Develop detailed validation schedules, define test plans, and coordinate execution across teams.
• Lead validation of PCIe Gen5/6 interfaces, high‑speed analog/mixed‑signal blocks (PLLs, SERDES, ADCs), and multi‑clock/reset domain logic.
• Perform hardware bring‑up, debug hardware‑software integration issues, and support board‑level/system‑level validation.
• Collaborate with hardware, firmware, and driver teams to isolate and root cause issues.
• Utilize scripting (Perl, TCL, shell scripts) to automate testing and manage regression environments.
• Analyze compliance with standards (PCIe, IEEE 802.3 Ethernet) and ensure robustness of physical layer implementations.
• Contribute to the development of SystemVerilog/UVM‑based validation environments and reusable test components.
• Drive issue resolution across cross‑functional teams and maintain ownership of validation deliverables.
• Mentor junior engineers, promote best practices, and introduce modern validation techniques to improve efficiency and coverage.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical or Computer Engineering (BSEE/MSEE).
• 8+ years of hands‑on experience in chip validation, silicon bring‑up, and test development.
• Proven expertise in validating PCIe Gen5/6, Ethernet PHY (IEEE 802.3), and SERDES‑based interfaces.
• Strong programming skills in C/C++, SystemVerilog, and Object‑Oriented Programming.
• In‑depth experience in firmware, driver, and microcontroller‑based SoC debug and integration.
• Familiarity with testbench development using UVM or equivalent environments.
• Skilled in scripting languages like PERL, TCL, Shell for automation and data analysis.
• Deep understanding of PLL, CDR, AMS, and analog/digital interface validation is a strong plus.
• Solid debugging expertise in RTL (Verilog/VHDL), hardware boards, and system software.
• Ability to work independently and across global time zones, with strong communication and leadership skills.

Preferred Skills:

• Experience in high‑speed analog validation, jitter analysis, and eye diagram interpretation.
• Familiarity with silicon failure analysis, debug probes, and lab equipment like oscilloscopes, logic analyzers.
• Working knowledge of regression management tools, Git, Jenkins, or similar CI/CD workflows.
• Understanding of signal integrity, board layout considerations, and compliance testing methodologies.

Why Join Us?

• Work on next‑gen, high‑performance silicon solutions shaping future technologies.
• Collaborate with world‑class engineering teams in a dynamic, innovative environment.
• Grow in a role that blends technical leadership, hands‑on engineering, and cross‑functional impact.