Silicon Validation Director

Mulya Technologies; India; On-site; INR 2,500,000 - 5,000,000; Full time

Job summary

Mulya Technologies is seeking a seasoned Silicon Validation Director to own end-to-end silicon bring-up and validation for next-generation SoCs. You will lead a cross-functional team across RTL, DV, firmware, and software to ensure first-pass silicon quality and production readiness.

You will drive validation strategy, test automation, and lab infrastructure while collaborating with external IP vendors and partners to meet aggressive tapeout milestones.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 18+ years of silicon/hardware validation experience, with 6+ years in a leadership role.
• Deep PCIe expertise (Gen 4/5/6) and compliance testing.
• Strong CXL validation experience and DDR5 memory validation.
• Proven leadership, collaboration, and project delivery skills.

Responsibilities

• Own full lifecycle of silicon bring-up and validation for next-gen SoCs.
• Lead cross-functional validation team; define test strategies and plans.
• Interface with design, firmware, and software teams for hand-off.
• Develop validation plans, coverage matrices, and sign-off criteria.
• Coordinate interoperability testing for PCIe, CXL, DDR5.
• Drive test automation and CI/CD for regression management.
• Mentor engineers and establish lab best practices.

Skills

PCIe

CXL

DDR5

RISC-V

Test Automation

Leadership

Team Management

Education

Bachelor’s/Master’s in Electrical/Computer Engineering

Tools

Teledyne LeCroy

Keysight

Spirent

Job description

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency unlocking unprecedented efficiency for AI training and inference at scale

our architecture is not just an incremental improvement its a foundational shift in how AI hardware is built for the futur

Silicon Validation Director

Location: Hydera

bad

Department: Silicon Engineering / Hardware Validation

Employment Type: Full-

Time

We are a semiconductor company pioneering high-performance interconnect and chip-tochip communication solutions. Our engineering teams push the boundaries of what is possible in silicon design, validation, and system integration. We are looking for a seasoned Silicon Validation Lead to join our R&D organization and drive end-to-end validation of complex SoC platforms.

Role Overview

As the Silicon Validation Director you will own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms that integrate PCIe, CXL, DDR5, RISC-V processors, Memory Fabric, PCIe Switch, and Caliptra Root of Trust (RoT) subsystems. You will lead a cross-functional validation team, define test strategies, and act as the primary technical interface between design, architecture, firmware, and system teams to ensure first-pass silicon quality and robust production readiness.

Key Responsibilities

• Silicon Bring-Up & Validation Lead pre- and post-silicon validation for complex SoCs encompassing PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5 memory subsystems, RISC-V processor cores, Memory Fabric, PCIe Switch, and Caliptr a RoT IP.
• Drive silicon bring-up from power-on through full functional validation, characterization, and compliance testing. Develop and own comprehensive silicon validation plans, test coverage matrices, and sign-off criteria aligned with tapeout and production milestones.
• Execute and manage compliance and interoperability testing against PCIe, CXL, JEDEC DDR5, and relevant security/RoT standards.
• Test Architecture & StrategyDefine test infrastructure architecture: board-level bring-up environments, FPGA prototypes, simulation correlation, and lab automation frameworks.
• Drive development of validation collateral including test plans, test suites, regression frameworks, and pass/fail criteria for all integrated subsystems.
• Establish coverage tracking dashboards and triage processes to systematically reduce validation escapes.
• Debug & Root Cause AnalysisLead deep-dive debugging of complex multi-layer failures spanning RTL, firmware, hardware, and system software. Utilize protocol analyzers, logic analyzers, oscilloscopes, and CXL/PCIe test equipment (e.g., Teledyne LeCroy, Keysight, Spirent) to isolate and characterise issues.
• Author and maintain detailed bug reports, failure analysis documents, and errata for silicon revisions.
• Team Leadership & CollaborationLead and mentor a team of validation engineers; set technical direction, review deliverables, and foster a culture of engineering rigor.
• Collaborate closely with RTL design, DV, firmware, and software teams to ensure seamless hand-off from pre-silicon simulation to physical silicon validation.
• Interface with external IP vendors, OEM/ODM partners, and compliance labs for interoperability and certification activities.
• Represent the validation team in architecture reviews, design reviews, and program planning meetings.
• Process & Continuous ImprovementChampion test automation and CI/CD integration for regression management.
• Drive lessons-learned processes across silicon spins and contribute to validation methodology improvements.
• Establish and maintain lab safety, equipment inventory, and test asset management best practices.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 18+ years of hands-on silicon validation or hardware validation engineering experience, with at least 6 years in a Manager/Lead or staff-level role.
• Deep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer characterization, and debug.
• Strong hands-on experience with CXL (1.1 / 2.0 / 3.0): memory semantic protocols, device types (Type 1/2/3), coherency mechanisms, and interoperability testing.
• Extensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC compliance, and RAS features.
• Solid experience .