Senior Verification Engineer - ASIC

Avant Garde; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Avant Garde is seeking a Senior ASIC verification engineer in Bengaluru to lead hands-on block, subsystem and chip-top verification. You will develop SystemVerilog and UVM environments, run mixed-signal device verification and oversee gate-level simulations across PVT corners.

Collaboration with analog and architecture teams, FPGA-based validation, and customer-debug support are part of the role. The candidate will also script in Perl, Python or Shell to automate tests and bring-up validation in

Qualifications

• 8–15 years hands-on verification experience in block, subsystem or chip-top level.
• Experience developing SystemVerilog and UVM environments and tests.
• Knowledge of mixed-signal devices and related verification approaches.

Responsibilities

• Develop SystemVerilog and UVM environments and tests.
• Verify block/subsystem/chip-top with gate-level simulations across PVT.
• Support DFT/ATPG simulations and lab bring-up.
• Script in Perl/Python/Shell for automation and test benches.
• Collaborate with analog and architecture teams; provide customer debugging support.

Skills

8-15 years experience

ASIC verification

collaboration

Tools

SystemVerilog

UVM

Perl

Python

Shell

Gate-level simulations

DFT

ATPG

FPGA validation

Job description

• Senior ASIC verification role requiring 8-15 years of hands-on block, subsystem and chip-top verification.
• The incumbent will develop SystemVerilog and UVM environments and tests, work on mixed-signal devices, implement RAL and functional and code coverage, run gate-level simulations across PVT corners and support DFT and ATPG simulations.
• Scripting in Perl, Python or Shell, collaboration with analog and architecture teams, FPGA-based validation, lab bring-up and customer-debug support are also required.
• This is a full-time work-from-office role in Bengaluru.