Senior Technical Staff Engineer - Verification

FHLB Des Moines; Bengaluru; On-site; INR 14,354,000 - 18,182,000; Full time

Job summary

Microchip Technology Inc. is seeking a Senior Technical Staff Engineer – Verification to lead IP-level verification for dsPIC products using formal verification and UVM testbenches.

The role is based in Chandler, Arizona and involves defining verification plans, building UVM and Formal environments, and driving coverage closure. You will mentor verification engineers, collaborate with SoC teams, and push for automated methodologies to shorten verification cycles while ensuring quality and

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Minimum 15 years of experience in functional verification.
• Strong expertise in SystemVerilog language, assertions, and UVM methodology.
• Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
• Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
• Strong communication, teamwork, and problem-solving skills.
• Highly motivated, detail-oriented, and committed to delivering quality results on time.

Responsibilities

• Architect, develop, and maintain UVM verification environments and Formal verification environments.
• Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
• Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
• Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
• Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.
• Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
• Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.

Skills

SystemVerilog

UVM

Formal verification

Assertions

RTL design

SoC architecture

Debugging

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

UVM testbenches

Formal verification environments

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Description

The dsPIC Business Unit is seeking a Senior Technical Staff Engineer – Verification to join our team in Chandler, Arizona. In this role, you will lead IP-level verification for dsPIC products using formal verification and UVM testbenches.

Key Responsibilities

• Architect, develop, and maintain UVM verification environments and Formal verification environments.
• Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
• Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
• Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
• Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.
• Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
• Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.

Requirements/Qualifications

• Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Minimum 15 years of experience in functional verification.
• Strong expertise in SystemVerilog language, assertions, and UVM methodology.
• Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
• Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
• Strong communication, teamwork, and problem-solving skills.
• Highly motivated, detail-oriented, and committed to delivering quality results on time.

Preferred Qualifications

• Demonstrated success in mentoring engineers and leading verification efforts across global teams.
• Experience driving methodology improvements and automation initiatives.

Travel Time: 0% - 25%