Senior Technical Staff Engineer-Software Design

HVAC Total FM Recruitment

Hyderabad

On-site

INR 4,500,000 - 7,500,000

Full time

3 days ago
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Job summary

Microchip Technology Inc. is seeking an FPGA Software Engineer to drive high-level and general synthesis techniques and boost FPGA design automation.

You will collaborate with architecture, place-and-route, timing analysis, and QA teams to advance QoR and next-generation FPGA capabilities. The role emphasizes developing scalable data structures and high-performance C++ software, supporting debugging, and contributing to automation, regression, and AI-assisted test generation workflows in a Linux

Qualifications

  • 20 years of EDA software experience required.
  • Excellent knowledge of FPGA architecture, FPGA flows and timing closure techniques.
  • Strong C++ programming, OO design, data structures and algorithms.

Responsibilities

  • Design, develop, implement, and verify algorithms for FPGA technologies.
  • Develop optimization techniques focused on timing, area, power, and QoR improvements.
  • Analyze FPGA designs to identify bottlenecks and improve QoR.
  • Collaborate with architecture and place-and-route teams for physical synthesis integration.
  • Participate in design and code reviews with feedback on software architecture.

Skills

C++
Algorithms
Data structures
OO design
Debugging
Linux

Education

Bachelor's or Master's in CS/EE

Tools

Verilog
VHDL
RTL synthesis
High-level synthesis
Linux tooling

Job description

Job Description:

FPGA Software Engineer

About the Position

This position is an excellent opportunity for an engineer passionate about high level and general synthesis technology and FPGA design automation. The role focuses on developing and enhancing the FPGA design flow, while also supporting architectural evaluation for future FPGA devices.

The engineer will work closely with FPGA architecture, place-and-route, timing analysis, and software QA teams to build next-generation capabilities with strong Quality of Results (QoR).

Responsibilities
  • Design, develop, implement, and verify algorithms for FPGA technologies.
  • Develop optimization techniques focused on timing, area, power, and overall QoR improvements.
  • Analyze customer and internal FPGA designs to identify bottlenecks and implement algorithmic enhancements.
  • Collaborate with FPGA architecture and place-and-route teams to support physical synthesis integration.
  • Participate in design and code reviews, providing feedback on software architecture and implementation approaches.
  • Develop scalable data structures and high-performance software components using modern C++.
  • Support debugging and root-cause analysis of issues in customer designs.
  • Create proof-of-concept implementations for benchmarking.
  • Contribute to automation, regression infrastructure, and validation environments for tool development.
  • Leverage AI-assisted methodologies to generate test cases, improve validation coverage, and accelerate development workflows.
Requirements / Qualifications
  • At least 20 years of experience in EDA software development.
  • Excellent knowledge of FPGA architecture, FPGA flows, and timing closure techniques.
  • Strong expertise in modern C++ programming, object-oriented design, data structures, and algorithms.
  • Hands-on experience in high level synthesis or RTL synthesis tool development.
  • Strong understanding of Verilog and VHDL.
  • Experience with optimizations, logic transformations, and netlist generation techniques.
  • Ability to analyze complex FPGA designs and improve QoR.
  • Strong debugging and problem-solving skills in large-scale software systems.
  • Experience developing high-performance software applications in Linux environments.
  • Exposure to AI-assisted development workflows and automated test generation is highly desirable.
  • Strong communication skills and ability to work effectively in a collaborative team environment.
Education

Bachelor's or Master's degree in Computer Engineering, Electrical or Electronics Engineering, Computer Science.

Travel Time

0% - 25%.

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