Fpga Design Engineer

Coreel Technologies; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Coreel Technologies in Bengaluru seeks an experienced FPGA/SoC technical lead to own architecture and RTL implementation for signal processing subsystems. You will drive design partitioning between FPGA fabric and embedded ARM cores, review RTL for timing/power, and guide synthesis, P&R, and bitstream generation for Xilinx platforms.

You will develop and verify DSP modules, integrate with ARM software, and mentor junior engineers while ensuring ISO-compliant processes and robust hardware

Qualifications

• Experience leading FPGA design and verification projects.
• Strong RTL design skills in VHDL/Verilog.
• Hands-on with Xilinx FPGA toolchain (Vivado/ISE) and timing closure.
• Exposure to Zynq/Zynq UltraScale+ platforms.
• DSP algorithms implemented in FPGA are a plus.

Responsibilities

• Own the FPGA design architecture and RTL implementation.
• Translate system requirements into FPGA architectures.
• Lead partitioning between FPGA fabric, embedded ARM cores, and external components.
• Review RTL for timing closure, power, and resource utilization.
• Guide synthesis, place-and-route, STA, and bitstream for Xilinx/AMD platforms.
• Lead root cause analysis for FPGA/hardware integration issues.
• Develop RTL modules for DSP, control, and high-speed interfaces.
• Integrate FPGA logic with embedded ARM software for SoCs (Zynq).
• Drive verification with ModelSim/XSIM; plan coverage and regression.
• Maintain design documentation, specs, interfaces, and timing analyses.
• Mentor junior engineers in RTL design and debugging practices.

Skills

RTL Design

Zynq SoC Experience

Scripting

FPGA Debugging

Mentor Team

Education

BE/BTech in Electronics/EE

Tools

Xilinx Tools

Job description

Role & responsibilities

Key Responsibilities

1. Technical Leadership

• Own the FPGA design architecture and implementation for assigned subsystems or projects.
• Translate high-level system requirements and signal processing algorithms into efficient FPGA architectures.
• Lead design partitioning between FPGA fabric, embedded ARM cores (for SoCs), and external components.
• Review and optimize RTL code for timing closure, power, and resource utilization.
• Guide the team in synthesis, P&R, STA, and bitstream generation for Xilinx/AMD platforms.
• Lead root cause analysis for FPGA/hardware integration issues.

2. Design & Development

• Develop RTL (VHDL/Verilog) modules for signal processing, control, and high-speed data interfaces.
• Implement and verify digital signal processing modules such as filters, modulators, encoders, and error correction blocks (LDPC, Turbo, etc.).
• Define and maintain FPGA design documentation architecture specs, interface definitions, implementation reports, and timing analysis records.
• Integrate FPGA logic with embedded ARM software for SoC-based systems (e.g., Zynq/Zynq UltraScale+).

3. Verification & Validation

• Develop and review simulation testbenches using ModelSim or XSIM.
• Drive functional verification, coverage, and regression test planning.
• Support hardware bring-up, integration testing, and validation using real-time signals and tactical radio platforms.

4. Process & Quality

• Ensure adherence to ISO 9001:2015 and internal FPGA design development processes.
• Conduct design reviews — input, output, verification, and change reviews — with documented MoMs.
• Collaborate with cross-functional teams (System, Firmware, Hardware, QA) to ensure seamless product integration.

5. Mentorship & Team Building

• Mentor junior engineers in RTL design, FPGA methodologies, and debugging practices.
• Provide technical guidance during code reviews, synthesis, and timing closure.
• Encourage continuous learning, reusability, and innovation in FPGA workflows.

Professional Skills:

• RTL design in VHDL/Verilog
• Xilinx tools for synthesis and implementation
• Thorough understanding of Xilinx FPGA’s
• Simulation and verification using ModelSim/XSIM
• Synthesis, place-and-route, static timing analysis, and constraint management
• Hands on with Zynq SoC or Zynq UltraScale+ platforms preferred
• Familiarity with scripting (Tcl/Python/Shell) for simulation & compilation automation
• Hardware Design: Logic Design & Debugging expertise
• Good to have implemented DSP algorithms in FPGA environment for Radar, wireless communication
• Good to have modelled the algorithms in Octave/MATLAB, generated test vectors, visualized data.
• Working knowledge on interfacing with ADCs and DACs and interpreting their performance.
• Configuration/Version control tools like SVN

Desired Attributes/ Soft skills

• Strong analytical and debugging skills at both RTL and board levels.
• Ability to architect modular and reusable FPGA designs.
• Effective communicator with a collaborative mindset across hardware, software, and system teams.
• Ownership-driven attitude with a focus on delivery excellence, decision making and design integrity.

Enthusiastic mentor fostering technical growth within the team.