Senior Technical Staff Engineer – Emulation

Microchip Technology Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Microchip Technology Inc. Bengaluru seeks an experienced hardware emulation architect to design RTL models and UVM-accelerations for EdgeAI and high-speed IPs.

You will integrate RTL with bare-metal firmware on emulation systems, drive end-to-end bring-up, and validate system-level platforms. The role requires 10+ years in hardware emulation, RTL design, and FPGA methodologies, with deep experience in PCIe, Ethernet, DDR, AMBA, and USB.

Qualifications

• Bachelor's degree in a technical field (BSEE/MSEE) or equivalent.
• Minimum 10+ years of progressive hardware emulation/RTL design experience.
• Expertise with Veloce platforms and UVM-acceleration for complex IPs.
• Strong RTL/Verilog/SystemVerilog and C/C++ programming skills.
• Deep knowledge of high-speed IPs (PCIe, Ethernet, DDRx, AMBA, SERDES, USB).
• Hands-on with FPGA architectures (Xilinx, Microsemi, Altera, Lattice) and hardware debugging.

Responsibilities

• Architect RTL models and UVM-acceleration for EdgeAI, PCIe, Ethernet, DDRC, etc.
• Develop CAD execution flows and high-fidelity emulation models on emulation platforms.
• Integrate RTL with bare-metal firmware on emulation systems for end-to-end bring-up.
• Develop system bring-up frameworks and debug RTL/firmware issues to accelerate time-to-market.
• Provide expert pre- and post-sale design support to customers and teams.

Skills

Analytical problem-solving

Communication

Education

BSEE / MSEE or equivalent

Tools

Verilog

SystemVerilog

C/C++

Veloce

UVM-acceleration

SystemC-DPI

RTL synthesis concepts

FPGA architectures

ARM Cortex

Debugging hardware boards

PCIe

Ethernet

SERDES

USB

Job description

Role Overview

The chosen candidate will be part of the FPGA Solutions Engineering team, working closely with internal engineering teams and external customers to architect, validate, and deliver next‑generation IP cores and system‑level platforms. This role bridges the gap between hardware architecture, advanced emulation methodologies, and firmware co‑design to enable early silicon‑equivalent bring‑up and accelerate time‑to‑market.

Key Responsibilities

• Architect Veloce RTL models and UVM‑acceleration for EdgeAI, PCIe, Ethernet, DDRC, etc.
• Build CAD execution flows, develop high‑fidelity emulation models, Veloce XACTORs, and system‑level use cases to drive deep performance and architectural validation on emulation platforms.
• Engineer shift‑left, end‑to‑end solution development by integrating hard and soft IP RTL with bare‑metal firmware on emulation systems.
• Develop system bring‑up frameworks, debug complex RTL/firmware issues, and accelerate time‑to‑market through comprehensive hardware‑software co‑validation.
• Provide technical feedback to Silicon Engineering, Software Engineering, and Marketing to enhance future product roadmaps; provide expert pre‑ and post‑sales design support to customers and sales forces.

Educational & Experience Requirements

• Education: BSEE / MSEE or equivalent technical degree.
• Experience: A minimum of 10+ years of progressive experience in hardware emulation, RTL design, FPGA methodologies, or HW/SW co‑verification.

Technical Expertise

• Strong proficiency with Veloce platforms, VirtuaLAB environments, UVM‑acceleration, and SystemC‑DPI testing methodologies.
• Proficient in Verilog, System Verilog, C/C++, RTL synthesis concepts.
• Deep understanding of high‑speed IPs including PCIe, Ethernet, DDR3/4/5, AMBA AHB/APB, SERDES, and USB.
• Strong foundation in DSP theory/processor architectures and embedded processors (e.g., ARM Cortex platforms) is highly desirable.
• Working knowledge of leading FPGA architectures (e.g., Microsemi, Xilinx, Altera, Lattice) and debugging physical boards.

Professional Skills

• Strong analytical and problem‑solving skills with a proven ability to debug complex, full‑stack hardware‑software issues and drive them to closure.
• Excellent written and verbal communication skills for authoring documentation, training modules, and presenting to executive customers.

Travel Time

0% - 25%