Senior IP Verification Engineer(IOMMU-N)

SiFive; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

SiFive is hiring for a verification engineer to contribute to CPU verification efforts. You will analyse architectural specs, create test plans, and build scalable UVM environments to verify IP blocks. The role involves constrained-random stimulus, debug using waveform tools, and tracking functional coverage.

Require 3+ years in DV, strong SystemVerilog/UVM skills, and knowledge of AXI/AHB protocols. Familiarity with CPU architectures (x86/ARM/RISC-V) is preferred and a background in scripting

Qualifications

• 3+ years of DV experience, preferably in CPU verification, with engineering degree.
• Proficiency in SystemVerilog and UVM methodology.
• Good knowledge of object-oriented programming.
• Experience with CPU architecture concepts (x86, ARM, or RISC‑V) and test writing.

Responsibilities

• Verification Planning: analyse specifications to define verification strategies and create test plans with coverage goals.
• Testbench Development: design scalable, reusable UVM environments.
• Stimulus & Constraint Generation: write constrained-random tests for IP stress tests.
• Debugging: perform root cause analysis using waveform viewers (Verdi, SimVision).
• Coverage Closure: define and track functional and code coverage; write covergroups/coverpoints.

Skills

SystemVerilog

Verilog

Python/Perl scripting

C/C++ programming

Object-oriented programming

Education

Bachelor’s or Master’s in Engineering

Tools

Verdi

SimVision

UVM

Job description

About SiFive As the pioneers who introduced RISC‑V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC‑V to the highest performance and most data‑intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimise and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data centre, mobile, and consumer. With SiFive, the future of RISC‑V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

Job Description:

Core Responsibilities:

• Verification Planning: Analyse architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.
• Testbench Development: Design and implement scalable, reusable, and constrained‑random verification environments using System Verilog and UVM (Universal Verification Methodology).
• Stimulus & Constraint Generation: Write complex sequences and constrained‑random tests to stress‑test the IP across corner cases.
• Debugging: Perform deep‑dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).
• Coverage Closure: Define and track functional and code coverage metrics. Write covergroups and coverpoints to ensure all architectural features have been exercised.

Languages :

• System Verilog
• Verilog
• Python/Perl (scripting)
• C/C++

Methodologies :

• UVM (highly preferred)
• OVM
• VMM

Protocols AXI, AHB:

• AXI
• AHB

Requirements:

• 3+ years of experience in DV preferably in CPU verification with Bachelor’s or Master’s in Engineering
• Proficiency in System Verilog and UVM methodology
• Very good object‑oriented programming skills
• Any CPU architecture knowledge (x86, ARM or RISC‑V) with test writing/test plan implementation experience
• Any scripting knowledge, preferably python
• Bus interface knowledge like AXI or PCIE Integration experience with third party VIPs like bus VIPs
• CPU micro‑arch knowledge

Additional Information:

• This position requires a successful background and reference checks and satisfactory proof of your right to work in: India
• Any offer of employment for this position is also contingent on the Company verifying that you are a authorised for access to export‑controlled technology under applicable export control laws or, if you are not already authorised, our ability to successfully obtain any necessary export license(s) or other approvals.
• SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
• Championed by leaders who chose to make a real difference, SiFive led the RISC‑V revolution—creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all.
• Now that we’ve made history, you have the opportunity to write the future.
• If you love to be challenged, you can join the best of the best and get rewarded for doing something that truly matters.

Check out our website and Glassdoor pages to learn more about SiFive’s phenomenal success and why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!)