Senior Staff Physical Design Floorplan

EnCharge AI; Bengaluru; Hybrid; INR 3,500,000 - 7,000,000; Full time

Job summary

EnCharge AI in Bengaluru seeks a Staff or Senior Staff Physical Design Engineer with deep Floorplanning expertise to own chip-top floorplan decisions for large-scale SoCs. You will bridge RTL/Systems and final GDSII, balancing power, performance and area across multi-million gate designs.

The role requires 10–14 years in Physical Design, proficiency with Innovus or IC Compiler II, strong scripting (Tcl/Python/Perl), and a track record of tape-outs at 7nm/5nm/3nm.

Qualifications

• Core Experience: 10+ years in Physical Design with tape-outs at advanced nodes (7nm/5nm/3nm).
• PDN Expertise: Model power-up sequences and multi-voltage domains.
• Floorplanning Savvy: Proficient in hierarchical physical design and top-level integration using Innovus or IC Compiler II.
• Analysis Skills: Thermal-aware PDN and implications of high-current density paths.
• Scripting: Proficient in Tcl, Python, or Perl for automation.

Responsibilities

• Architectural Floorplanning: Lead chip-level floorplanning for multi-million gate designs.
• EMIR Mastery: Perform IR-drop and Electromigration analysis and propose fixes.
• Cross-Functional PPA Trade-offs: Collaborate with RTL and Architecture; influence micro-architecture for physical outcomes.
• Methodology Development: Establish automated flows for floorplanning and PDN synthesis.

Skills

Floorplanning

PPA trade-offs

Scripting (Tcl/Python/Perl)

RTL-to-GDSII interface

Cross-functional collaboration

Education

B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent

Tools

Innovus

IC Compiler II

Job description

Staff/Senior Staff Physical Design Floorplan (Hybrid-2 days office/3 days home )

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Staff/Senior Staff Physical Design Floorplan

Experience: 10-14 Years

Location: Bangalore/2 days to work

Department: RTL-to-GDSII / Physical Implementation

Role Overview

We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with a specialized mastery of Floorplanning design. You won't just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum.

As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.

Key Responsibilities

• Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs.
• EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose architectural or physical fixes that don't compromise timing.
• Cross-Functional PPA Trade-offs: Collaborate directly with RTL and Architecture teams. You will use "Design Thinking" to influence the micro-architecture, suggesting changes to bus widths, pipeline stages, or memory configurations to optimize physical outcomes.
• Methodology Development: Establish best practices and automated flows for floorplanning and PDN synthesis to be used by the wider implementation team.

Technical Requirements

• Core Experience: 10+ years in Physical Design with a proven track record of multiple successful tape-outs at advanced nodes (7nm, 5nm, or 3nm).
• PDN Expertise:Ability to model complex power-up sequences and multi-voltage domains.
• Floorplanning Savvy: Deep proficiency in hierarchical physical design and top-level integration using industry-standard tools (Innovus or IC Compiler II).
• Analysis Skills: Strong understanding of thermal-aware PDN and the physical implications of high-current density paths.
• Scripting: Advanced proficiency in Tcl, Python, or Perl to automate complex floorplanning tasks and data analysis.

Behavioral Attributes

• Critical Thinker: You don't just follow a recipe. You question constraints and look for "hidden" PPA gains.
• Design Thinking: Ability to empathize with the challenges of upstream (RTL) and downstream (Sign-off) teams to create a holistic solution.
• Influence: You can articulate technical trade-offs to stakeholders,

Education

• B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent.