Senior Staff Physical Design Engineer

EnCharge AI; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

EnCharge AI in Bengaluru seeks a Senior Staff Physical Design Engineer with deep chip-level implementation experience using Cadence tools to drive timing closure and low-power design.

You will work on top-level and block-level physical design, develop scripts (TCL/Python) for automation, and verify power grids with EM/IR checks, contributing to a scalable in-memory AI hardware platform.

Qualifications

• 10–14 years of experience in physical design.
• Hands-on experience with Cadence tools.
• Strong understanding of timing concepts and timing-closure techniques.
• Experience with top-level and block-level physical design; hierarchical floorplanning is a plus.
• Proficiency in low-power design concepts and debugging.
• Experience with EM/IR checks and power grid verification.
• Strong scripting skills in TCL or Python for automation.
• Understanding of process concepts for physical verification.
• Experience with PD methodology and flow setup.
• PD-related experience in PDK management or foundry tapeout is a plus.

Skills

Scripting (TCL/Python)

Physical design

Timing closure

Low-power design

Floorplanning

Power integrity

EM/IR checks

Tools

Cadence tools

Job description

Title: Senior Staff Physical Design Engineer

About Company:

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge's robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Role

We are seeking a highly experienced Senior Staff Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.

Qualifications

• 10-14 years of experience in physical design (excluding other areas such as logic design or CAD).
• Strong understanding of EDA implementation for chip design, with hands-on experience in Cadence tools (must-have).
• Strong knowledge of timing concepts and timing closure techniques for chip design.
• Experience with both top-level and block-level physical design is required; experience with hierarchical floorplanning is a plus.
• Proficiency in low-power design concepts and debugging is necessary.
• Experience with EM/IR checks, debugging, and issue resolution, including power grid verification, is required.
• Strong scripting skills in TCL or Python for automation are important.
• Understanding of process concepts is needed for physical verification as part of routing tasks.
• Experience with physical design methodology and flow setup is preferred; this role will involve advanced flow evaluations.
• Additional experience in areas such as PDK management or foundry tapeout processes is a plus