Senior Physical Design Engineer

EnCharge AI; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

A leading AI technology company in Bengaluru seeks a Senior Physical Design Engineer with 4–7 years of experience for advanced silicon projects. The role demands a strong driver who can take ownership of complex partitions and optimize PPA through automation and deep analysis. Candidates should be proficient in Tcl and Python, have experience with Cadence tools, and possess strong debugging skills. This position offers the opportunity to work independently in a collaborative environment.

Qualifications

• 4–7 years of experience in Physical Design with at least 2–3 successful tape-outs.
• Solid hands-on experience with industry-standard EDA tools.
• Proficient in Tcl and Python for automation.

Responsibilities

• Lead the physical implementation of complex blocks from Synthesis to Sign-off.
• Optimize PPA recipe through deep analysis of timing and power profiles.
• Automate tasks using Tcl and Python to enhance efficiency.
• Resolve DRC/LVS and timing violations independently.
• Collaborate with RTL and DFT teams to optimize design from the start.

Skills

Physical Design expertise

Tcl and Python proficiency

Debugging in STA

Automation mindset

Analytical skills

Tools

Cadence Innovus

Cadence Tempus

Job description

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Title

Senior Physical Design Engineer

Experience

4–7 Years

The Role

We are looking for a high-energy, technically curious Physical Design Engineer to join our advanced silicon team. This isn't a role for someone who wants to just "push buttons" on a vendor flow. We need a driver—someone with 4–6 years of experience who has lived through the trenches of quality tape-outs and is hungry to take full ownership of complex partitions. You will be expected to work with a high degree of independence, using your analytical skills to bridge the gap between a standard recipe and a world-class PPA result. You should be comfortable following expert lead direction while maintaining the "question the status-quo" mindset when you see a more efficient path.

Key Responsibilities

• Partition Ownership: Lead the physical implementation of complex blocks from Synthesis and Floor-planning through to CTS, Routing, and Sign-off.
• PPA Recipe Development: Don't just run the flow—optimize it. You will perform deep-dive analysis on timing paths, power profiles, and congestion to derive custom optimization strategies.
• Automation-First Mindset: Use Tcl and Python to automate repetitive tasks, build custom analysis scripts, and enhance the efficiency of the physical design environment.
• Independent Convergence: Take a partition from "dirty" RTL to a clean GDSII, resolving complex DRC/LVS, IR drop, and timing violations with minimal supervision.
• Cross-Functional Collaboration: Work closely with RTL and DFT teams to "left-shift" physical constraints, ensuring the design is optimized for routing and timing from the start.

Technical Requirements

• Experience: 4–7 years in Physical Design with at least 2–3 successful tape-outs.
• Tool Mastery: Solid hands-on experience with industry-standard EDA tools—Cadence Innovus/Tempus.
• Automation: Proficient in Tcl (for tool control) and Python (for data parsing and flow automation).
• PPA Skills: Proven ability to analyse and improve Power, Performance, and Area through floor-planning and placement tuning.
• Analysis: Strong debugging skills in STA (Static Timing Analysis), EM/IR, and Physical Verification (DRC/LVS/ERC).

The Ideal Candidate Profile

• High "Workability" Quotient: Coachable, can execute complex instructions, and flags inefficient processes.
• The "Detective" Mindset: When a tool fails or timing won't close, digs into logs and data for root cause.
• Driven & Independent: "Get it done" attitude, unblocks themselves through research and experimentation.
• Curiosity: Understands the psychology of the tool and drives it as an expert driver.