Principal Physical Design Engineer (RTL-to-GDSII)

EnCharge AI; Bengaluru; Presencial; INR 2.500.000 - 3.500.000; Jornada completa

Descripción de la vacante

A leading AI hardware company based in Bengaluru is looking for a Principal Physical Design Engineer with 14+ years of experience. You will lead complex designs from synthesis to sign-off, optimizing power, performance, and area using Cadence tools. The ideal candidate has experience with sub-5nm tape-outs and is proficient in Tcl and Python for custom tool development. Join a team that shapes the future of silicon design and works on cutting-edge nodes.

Formación

• 14+ years in Physical Design with a proven track record of multiple sub-5nm tape-outs.
• Proficiency in developing custom flow wrappers and data-mining tools for PPA analysis.
• Expert knowledge in STA, PV, and PI methodology.

Responsabilidades

• Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off.
• Analyze and optimize PPA by utilizing the interplay between library cells and tool engines.
• Establish a robust methodology that minimizes manual iterations.

Conocimientos

Experience in Physical Design

Mastery of Cadence Innovus

Proficiency in Tcl and Python

Deep understanding of sub-5nm physics

Expert-level knowledge in Static Timing Analysis

Herramientas

Cadence Innovus

Cadence Digital Suite

Tempus

Joules

Pegasus

Voltus

Descripción del empleo

Principal Physical Design Engineer (RTL-to-GDSII)

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Title: Principal Physical Design Engineer (RTL-to-GDSII)

Experience:14+ Years

The Vision

We are seeking aPrincipal Physical Design Engineerwho thrives on complexity and rejects the "black box" approach to EDA tools. This role is for aFirst Principles thinkerwho questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII.

Key Responsibilities

• Full-Flow Ownership:Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using theCadence Digital Suite.
• PPA Optimization:Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.
• Methodology & Scalability:Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.
• Cross-Functional "Left-Shift":Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.
• Bottleneck Elimination:Identify "drag" in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.

Technical Qualifications

Experience

14+ years in Physical Design with a proven track record of multiplesub-5nmtape-outs.

Tool Suite

Mastery ofCadence Innovus, Tempus, Joules, Pegasus, and Voltus.

Advanced Nodes

Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET and IR/EM challenges.

Sign-off

Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.

Scripting

Proficiency inTcl and Pythonto develop custom flow wrappers and data-mining tools for PPA analysis.

• Holistic Thinking:You look at the "Big Picture." You solve timing by fixing the floorplan or the RTL/ARCH
• Influence & Rapport:You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.
• Critical Thinking:You operate on first principles. You don't just follow a vendor's "Best Practices" if they don't make sense for our specific architecture.
• Mentorship:You act as a force multiplier, elevating the technical competence of the entire PD team.

Why Join This Team?

In this role, you aren't just a "user" of tools; you are an engineer who shapes how silicon is built. You will have the autonomy to overhaul legacy flows and the resources to execute on cutting-edge nodes that define the industry's future.