Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

Google LLC; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Google LLC in Bengaluru is seeking a Senior Silicon Engineer focused on HBM memory subsystem design, integration and validation. You will drive microarchitecture, implement high-quality RTL for memory controllers, and collaborate with DV teams to enhance test plans and coverage.

The role involves leading interface with DFI, JEDEC specs, ATE bring-up, and mentoring engineers while advancing TPU-related ASICs powering AI/ML workloads across data centers. In-person interviews are typically required.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in memory subsystem design, integration or verification.
• Experience with DRAM protocols (HBM2e/HBM3/HBM4 or DDR/LPDDR4x/5/5X) including JEDEC timing, refresh and training sequences.
• Experience with the DFI controller-to-PHY interface, leading a feature or IP block, and mentoring engineers.
• Experience in SystemVerilog RTL, simulation and debug flows.

Responsibilities

• Define microarchitecture and develop high-quality RTL for memory controller frontends, guiding implementation trade-offs across performance, area, power, timing, and configurability for multi-channel and pseudo-channel configurations.
• Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, owning quality closure and schedule from concept to tapeout.
• Collaborate with DV teams to build test plans, improve coverage, and validate design intent (UVM, emulation, ECC/RAS error injection).
• Lead and support ATE testing, first-silicon lab bring-up, and physical characterization of the HBM PHY and controller across PVT corners.
• Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, methodology, and systematic root-cause debug.

Skills

Memory subsystem design

DRAM protocol expertise

DFI interface

SystemVerilog RTL

UVM methodology

Emulation-based validation

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science

Master's degree or PhD in Electrical Engineering / Computer Engineering / Computer Science

Job description

Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

Share Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in memory subsystem design, integration or verification.
• Experience with DRAM protocols (HBM2e/HBM3/HBM4 or DDR/LPDDR4x/5/5X) including Joint Electron Device Engineering Council (JEDEC) timing, refresh and training sequences.
• Experience with the DFI controller-to-PHY interface, leading a feature or IP block, and mentoring engineers.
• Experience in SystemVerilog RTL, simulation and debug flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience delivering configurable, reusable IP-parameterization, release packaging, integration guides and customer-facing documentation.
  
• Experience integrating third-party controller and PHY IP (Rambus, Cadence/Synopsys class) into production silicon.
• Experience with SECDED per pseudo-channel, Reed–Solomon symbol correction, error queues, lane/row repair, address-folded CRC.
• Experience with UVM methodology and emulation-based pre-silicon validation, and familiarity with memory telemetry and Silicon Lifecycle Management (SLM) — per-pseudo-channel counters, link availability, continuous eye-opening monitors.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, and physical design to deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define microarchitecture and develop high-quality RTL for memory controller frontends, guiding implementation trade-offs across performance, area, power, timing, and configurability for multi-channel and pseudo-channel configurations.
• Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, owning quality closure (DFI pipe wrappers, clock/reset, PLL references, sideband bridging) and schedule from concept to tapeout.
• Collaborate with DV teams to build test plans, improve coverage, and validate design intent (UVM, emulation, ECC/RAS error injection), while tracking JEDEC specs and memory conferences for the latest HBM trends.
• Lead and support ATE testing, first-silicon lab bring-up, and physical characterization of the HBM PHY and controller across PVT (process, voltage, temperature) corners.
• Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, methodology, and systematic root-cause debug.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.