Senior Silicon Design Verification Engineer Google Cloud

Google; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Google Bengaluru is seeking a senior verification engineer to own the full verification lifecycle for TPU hardware projects. You will design and implement constrained-random testbenches, verify with SystemVerilog, and drive coverage to closed states across AI/ML workloads.

You'll collaborate with design and verification teams on IPs/SoCs for networking-related accelerators, focusing on performance, accuracy, and reliability for next-generation hardware platforms.

Qualifications

• 8 years of verification experience with RTL-level digital logic using SystemVerilog or Specman/E.
• Experience verifying IP/subsystem/SoCs in networking, including packet processing and bandwidth management.
• Experience with standard IP components/interconnects verification (e.g., microprocessor cores, memory subsystems).

Responsibilities

• Plan the verification of digital design blocks by understanding the design spec and collaborating with design engineers to identify verification scenarios.
• Create constrained-random verification environments using SystemVerilog; verify designs with SystemVerilog Assertions and formal tools.
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and progress toward tape-out.

Skills

RTL verification using SystemVerilog/

Digital logic verification

Networking IP/SoC verification

Education

Bachelor's degree in Electrical/Computer/CS or related field

Masters or PhD in EE/CE/CS (preferred)

Tools

SystemVerilog

Specman

AI/ML accelerators experience

Job description

Job Description:

Minimum qualifications:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
• Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, congestion control.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Preferred qualifications:

• Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with industry-standard simulators, revision control systems, and regression systems.
• Experience in Artificial Intelligence/Machine Learning (AI/ML) accelerators or vector processing units.
• Experience with the full verification life cycle.
• Excellent problem-solving and communication skills.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities:

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology. Verify designs with SystemVerilog Assertions and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements: