Silicon Design Verification Engineer, TPU, Google Cloud

Google; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

A leading tech company in Bengaluru is looking for a Silicon Design Verification Engineer to drive verification for cutting-edge TPU technology powering AI/ML applications. The role requires strong skills in verification methodology (UVM) and SystemVerilog, along with a Bachelor's degree in Electrical Engineering. The successful candidate will collaborate closely with design engineers, plan verifications, and ensure the reliability of TPU hardware. This position offers an exciting opportunity to shape the future of AI/ML hardware acceleration.

Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience with verification methodology such as UVM.
• 2 years of experience verifying Intellectual Property (IP) designs.

Responsibilities

• Plan the verification of digital design blocks.
• Identify and write coverage measures for stimulus and corner cases.
• Debug tests with design engineers.

Skills

Verification methodology (UVM)

SystemVerilog

Problem solving

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree in related field

Tools

Industry-standard simulators

Version control systems

Regression systems

Job description

Silicon Design Verification Engineer, TPU, Google Cloud

In this role you’ll shape the future of AI/ML hardware acceleration by driving cutting‑edge TPU technology that powers Google’s most demanding AI/ML applications. You will own the full verification lifecycle—from verification planning and test execution to coverage closure—while collaborating with design and verification engineers to ensure reliability and performance of TPU hardware for AI workloads.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience with verification methodology such as Universal Verification Methodology (UVM).
• 2 years of experience verifying Intellectual Property (IP) designs such as SoC, vector CPUs, etc.
• Experience with SystemVerilog, SystemVerilog Assertions (SVA), and functional coverage.

Preferred qualifications

• Master’s degree in Electrical Engineering or a related field.
• Experience with industry‑standard simulators, revision control systems, and regression systems.
• Experience with the full verification lifecycle.
• Experience in AI/ML Accelerators or vector processing units.
• Excellent problem solving and communication skills.

Responsibilities

• Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
• Identify and write coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Measure verification holes to track progress toward tape‑out.
• Create a constrained‑random verification environment using SystemVerilog and UVM.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .