Senior Principal Engineer, DFT

Arm; Bengaluru; Hybrid; INR 3,500,000 - 5,000,000; Full time

Job summary

Arm’s Central Engineering DFT Architecture and Methodology team shapes the future of Design-for-Test across Arm IPs and SoCs. You will drive DFT architecture, methodologies, and verification, collaborating with architecture, verification, and physical design teams to deliver robust test solutions.

You will engage with EDA vendors, contribute to technical publications, and mentor project teams, influencing broader standards in the industry.

Qualifications

• Extensive experience in Design-for-Test architecture and implementation.
• Strong understanding of modern SoC DFT methodologies including scan, ATPG, and at-speed testing.
• Experience with memory and logic BIST, JTAG/IJTAG standards, and DFT verification.
• Proven ability to develop reusable DFT methodologies or automation.

Responsibilities

• Define DFT architecture for next-generation Arm IPs and SoCs.
• Develop scalable DFT methodologies and flows across engineering groups.
• Evaluate emerging DFT technologies and guide investigations.
• Collaborate with architecture, implementation, verification and physical design teams.
• Work with EDA vendors to influence roadmaps and drive adoption.

Skills

DFT architecture

Scan architecture

ATP G

At-speed testing

Memory BIST

Logic BIST

JTAG / IEEE 1149.1

IJTAG / IEEE 1687

DFT verification

Scripting: Perl/Tcl/Python

Linux/Unix

Technical leadership

Communication skills

Electronic/Computer engineering

Education

Degree in Electronic Engineering or Computer Engineering

Tools

Siemens Tessent

Synopsys DFT solutions

Cadence DFT solutions

Job description

Job Overview

Arm's Central Engineering DFT Architecture and Methodology team defines the future of Design-for-Test across Arm's CPUs, GPUs, System IP, AI accelerators and next-generation SoCs. The team develops DFT architectures, methodologies and implementation flows that enable high-quality, scalable test solutions across soft IP, hard macros, test chips and complex multi-die SoCs.

Arm's Central Engineering DFT Architecture and Methodology team defines the future of Design-for-Test across Arm's CPUs, GPUs, System IP, AI accelerators and next-generation SoCs. The team develops DFT architectures, methodologies and implementation flows that enable high-quality, scalable test solutions across soft IP, hard macros, test chips and complex multi-die SoCs. Working at the forefront of semiconductor innovation, you will collaborate with product teams, system architects, design engineers and EDA vendors to shape DFT technologies several years ahead of production. This is a highly technical architecture role with significant influence across Arm and the broader semiconductor ecosystem.

Responsibilities

• Define DFT architecture for next-generation Arm IPs and SoCs, including emerging AI and hyperscale computing products.
• Develop and drive scalable DFT methodologies and implementation flows used across multiple Arm engineering organizations.
• Evaluate emerging DFT technologies and lead technical investigations to solve future product challenges.
• Collaborate with architecture, implementation, verification and physical design teams to define robust DFT solutions.
• Work closely with EDA vendors to influence product roadmaps, evaluate new capabilities and drive adoption of new technologies.
• Produce architecture specifications, methodology documentation and deployment guidance.
• Provide technical leadership and mentorship across project teams.
• Support strategic engagements with customers, ASIC partners and industry standards bodies where appropriate.
• Contribute to technical publications, patents and industry conferences.

Required Skills and Experience

• Principal or Senior Principal level engineer with extensive experience in Design-for-Test architecture and implementation.
• Strong understanding of modern SoC DFT methodologies including:
• Scan architecture and scan compression
• ATPG and fault simulation
• At-speed testing
• Memory BIST
• Logic BIST
• JTAG / IEEE 1149.1
• IJTAG / IEEE 1687
• DFT verification and debug
• Experience developing reusable DFT methodologies or automation rather than project-specific solutions.
• Experience evaluating and deploying Siemens Tessent, Synopsys and/or Cadence DFT solutions.
• Strong scripting skills (Perl, Tcl and/or Python) together with Linux/Unix expertise.
• Excellent problem-solving and analytical skills.
• Strong communication skills with the ability to influence technical direction across multiple engineering teams.
• Degree (or equivalent) in Electronic Engineering, Computer Engineering or related discipline.

Nice To Have Skills and Experience

• Experience defining DFT architecture for large-scale SoCs.
• Experience with heterogeneous compute systems, AI accelerators or hyperscale computing products.
• Knowledge of IEEE 1500, IEEE 1838 and advanced IJTAG methodologies.
• Experience with Streaming Scan Network (SSN) and chiplet/3DIC architectures.
• Familiarity with silicon bring-up and production test.
• Experience working directly with EDA vendors on new technology development.
• Knowledge of synthesis, STA and physical implementation considerations for DFT.
• Experience with formal verification and simulation methodologies.
• Record of patents, conference publications or contributions to industry standards.

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.