Staff Engineer -DFT

Arm Limited; India; Hybrid; INR 3,500,000 - 6,000,000; Full time

Job summary

Arm Limited is seeking an experienced DFT Engineer to lead the verification of mixed-signal IP blocks and drive ATE pattern development on silicon.

You will own DFT feature verification across SoC levels, debug complex issues, and collaborate with cross-functional teams during pre- and post-silicon phases. A strong background in JTAG/iJTAG, Tessent tools, and pattern development is required.

Qualifications

• 10+ years of hands-on experience in DFT.
• Experience with verification of mixed-signal blocks from a DFT perspective.
• Strong understanding of ATE, pattern generation and debug flows.

Responsibilities

• Perform DFT verification of mixed-signal IP blocks in complex SoC.
• Own verification and debug of DFT features across block and SoC levels.
• Develop, verify, and debug ATE test patterns and drive pattern bring-up on silicon.
• Perform ATE pattern debug and stabilization including root-cause analysis of failures.
• Work with JTAG and iJTAG architectures and verification flows.
• Develop and maintain PDL for embedded instruments and iJTAG networks.
• Generate, validate, and debug DFT patterns using Tessent tools.
• Debug complex pattern, timing, protocol, and DFT issues across sim and ATE.
• Collaborate with DFT, design, verification, PD, and test teams.

Skills

DFT verification

Mixed-signal IP

JTAG/iJTAG

Pattern development

Tessent tools

Tools

Siemens Tessent

ATE patterns

Job description

Job Description –

Experience: 10+ Years of experience

Role: Mixed Signal DFT lead/engineer

Role Overview

We are looking for an experienced DFT Engineer with 10+ years of semiconductor industry experience and strong hands-on expertise in DFT verification of mixed-signal blocks, Pattern debug on ATE, and Tessent-based pattern generation. The ideal candidate will have a strong understanding of mixed signal IP like SERDES, Sensors, non-volatile memory (effuse/otp/), JTAG/iJTAG architectures, PDL development for Pattern development, in-depth understanding on ATE and The candidate should be capable of independently debugging complex DFT and production-test issues and driving them to closure.

Key Responsibilities

• Perform DFT verification of mixed-signal IP blocks in complex SoC
• Own verification and debug of DFT features across block and SoC levels.
• Develop, verify, and debug ATE test patterns and drive pattern bring-up on silicon.
• Perform ATE pattern debug and stabilization, including root-cause analysis of simulation-to-silicon and tester-related failures.
• Work extensively with JTAG (IEEE 1149.1) and iJTAG (IEEE 1687) architectures and associated verification flows.
• Develop and maintain PDL (Procedural Description Language) for embedded instruments and iJTAG networks.
• Generate, validate, and debug DFT patterns using Siemens Tessent tools.
• Debug complex pattern, timing, protocol, and DFT infrastructure issues across simulation and ATE environments.
• Collaborate closely with DFT, design, verification, physical design, product engineering, and test engineering teams during pre-silicon and post-silicon phases.
• Drive technical issues independently from initial investigation through root-cause identification and final resolution.

Required Skills & Experience

• 10+ years of hands-on experience in DFT, DFT verification.
• Strong hands-on experience with verification of mixed-signal blocks from a DFT perspective.
• In-depth understanding of ATE architecture, test programs, pattern formats, and pattern execution/debug flows.
• Proven experience in:
  • Loopback test verification for high speed SERDES blocks (like UCIe, DDR PHY, PCIE/Ethernet, USB) based on BIST
  • Sensors and calibration procedures
  • Lane repair schemes
  • ATE pattern bring-up and debug
  • Pattern stabilization
  • Failure analysis and root-cause debugging
  • Test-time reduction and optimization
  • Know-how on SCAN & MBIST is plus
• In-depth understanding of JTAG and iJTAG protocols, including IEEE 1149.1 and IEEE 1687.
• Strong experience in developing pattern specifications, PDL development and debug using Siemens Tessent tools.
• Good understanding of DFT concepts such as test access mechanisms, embedded instruments
• Excellent analytical and problem-solving skills, with the ability to debug complex cross-domain issues.
• Ability to work independently and take complete ownership of technical deliverables.
• Strong communication skills and ability to collaborate effectively with geographically distributed engineering teams.

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Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.