Senior Principal Engineer - Design Verification

Upscale, Inc.; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Upscale, Inc. is seeking a visionary Senior Principal DV Engineer to define the global verification strategy for massive-scale networking SoCs.

This elite leadership role will set the overarching verification methodology and drive cross-functional alignment from architecture to post-silicon, pioneering next-generation verification technologies. You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while mentoring principal

Qualifications

• Define the overarching verification methodology for multi-million gate networking SoCs.
• Drive cross-functional alignment from architecture to post-silicon.
• Mentor engineers and lead implementation of novel verification technologies.

Responsibilities

• Define, architect, and govern the verification roadmap for large networking SoCs.
• Drive adoption of FPV, emulation, and shift-left strategies.
• Establish quality metrics and sign-off criteria across the project lifecycle.
• Review specs with Silicon Architects to optimize micro-architecture for testability.
• Mentor Principal engineers and technical leads across the site.

Skills

SoC Verification

FPV

Hardware Emulation

Formal Methods

Mentorship

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world's most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking-where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you're looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI-Upscale is where you can produce meaningful work at the frontier-and operate at a high standard.

Experience Level: 17+ Years (or 15+ with exceptional strategic track record)

Location: Bangalore, India (On-Site)

Position Type: Full-Time

About the Role

We are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.

Key Responsibilities

• SoC Verification Strategy: Define, architect, and govern the overarching verification roadmap and methodology for full-scale, multi-million gate networking SoCs.
• Methodology Innovation: Drive the adoption of advanced methodologies. Seamlessly integrate Formal Property Verification (FPV), hardware emulation, and advanced shift-left strategies into the standard SoC timeline.
• High-Level Governance: Establish, track, and enforce rigorous quality metrics and sign-off criteria across the entire project lifecycle, ensuring zero-defect silicon.
• Architectural Influence: Work directly with Silicon Architects and Design Directors to review specs, optimize micro-architecture for testability/verifiability (DFV), and mitigate risk early.
• Organizational Mentorship: Mentor Principal engineers and technical leads across the site. Champion best practices