Senior Physical Design Engineer-Synthesis & STA

EnCharge AI; Bengaluru; Hybrid; INR 1,200,000 - 1,800,000; Full time

Job summary

EnCharge AI seeks a Senior Synthesis & STA Engineer to own end-to-end logic synthesis and signoff for key blocks and sub-chips. You will bridge front-end RTL and back-end physical design, ensuring synthesis meets aggressive target frequencies and quality standards.

You will advise RTL teams, optimize netlists, and progressively expand into PNR, STA, and full-chip timing convergence. A strong background in Verilog/SystemVerilog and Cadence Genus is essential.

Qualifications

• 5–8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
• Hands-on experience with industry-standard synthesis tools, strong preference for Cadence Genus.
• Proficiency with STA signoff tools (e.g., Tempus, PrimeTime).
• Strong knowledge of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
• Ability to analyze datapath architectures and suggest RTL changes to reduce logic depth.
• Proficiency in Tcl, Python, or Perl for automation and reporting.

Responsibilities

• Own the complete logic synthesis process for designated blocks and sub-chips to optimize area, power, and performance.
• Define, execute, and monitor rigorous sanity checks to achieve high-quality Synthesis Signoff.
• Collaborate with RTL designers to deliver a clean, linted netlist before handoff.
• Deep-dive into timing paths to ensure Levels of Logic (LOL) meet high-frequency targets.
• Provide RTL coding guidelines and micro-architecture inputs to improve synthesis outcomes.
• Expand into physical design adjacencies, participating in PNR, STA, and full-chip timing convergence.

Skills

Synthesis ownership

Quality signoff

RTL collaboration

Frequency optimization

RTL & logic fundamentals

Netlist optimization

Scripting automation

Cross-functional communication

Tools

Cadence Genus

Tempus

PrimeTime

Job description

Location: Bangalore INDIA Hybrid (2 days office/3 days home) / Remote(any where in India)

www.EnchargeAi.com

The 10 Hottest Semiconductor Startups Of 2025 (So Far)

https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far?page=11

Location : Bangalore ( Hybrid- 2days office, 3 days-home)

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Title: Senior PD engineer : Synthesis & STA

Role Overview

We are seeking a highly skilled VLSI Synthesis & STA Specialist to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips.

In this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams.

You will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist.

This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.

Key Responsibilities

• Synthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.
• Quality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.
• RTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.
• Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.
• Micro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.
• Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.

Required Skills & Qualifications

• Experience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
• EDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.
• Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.
• RTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
• Netlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.
• Scripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.
• Cross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.

Preferred Qualifications

• Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.
• Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
• Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.