Senior Physical Design Engineer

Allegis Group; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Allegis Group is hiring for a Tile PNR Engineer in Bangalore. The role demands 4+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows.

You will own end-to-end physical design of SoC/IP tiles from floorplan to signoff, drive timing, power, area, congestion, and physical verification closure, and collaborate with FE, FCNL, Clock, Power, and PV teams for design convergence.

Qualifications

• 4+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows.
• Own end-to-end physical design of SoC/IP tiles from floorplan to signoff.
• Drive timing, power, area, congestion, and physical verification closure.
• Collaborate with FE, FCNL, Clock, Power, and PV teams for design convergence.
• Debug implementation issues and develop automation/scripts to improve productivity.
• Lead critical tile execution and mentor junior engineers on PD methodologies.

Responsibilities

• Own end-to-end physical design of SoC/IP tiles from floorplan to signoff.
• Drive timing, power, area, congestion, and physical verification closure.
• Collaborate with FE, FCNL, Clock, Power, and PV teams for design convergence.
• Debug implementation issues and develop automation/scripts to improve productivity.
• Lead critical tile execution and mentor junior engineers on PD methodologies.

Skills

ASIC/SoC timing analysis

Physical design flows

End-to-end PD ownership

Automation scripts

Team mentoring

Cross-functional collaboration

Education

Bachelors or Masters in Electrical/Electronics Engineering / VLSI / Microelectronics

Job description

Hiring for Physical Design

Location: Bangalore

YOP: 4+ years

For Product based company

Top 3 skills:

• 4+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows. Own end-to-end physical design of SoC/IP tiles from floorplan to signoff.
• Drive timing, power, area, congestion, and physical verification closure.
• Collaborate with FE, FCNL, Clock, Power, and PV teams for design convergence.
• Debug implementation issues and develop automation/scripts to improve productivity.
• Lead critical tile execution and mentor junior engineers on PD methodologies.

JD: Tile PNR Engineer

• Own end-to-end physical design of SoC/IP tiles from floorplan to signoff.
• Drive timing, power, area, congestion, and physical verification closure.
• Collaborate with FE, FCNL, Clock, Power, and PV teams for design convergence.
• Debug implementation issues and develop automation/scripts to improve productivity.
• Lead critical tile execution and mentor junior engineers on PD methodologies.

Preferred Experience & Qualifications

Bachelors or Masters degree in Electrical/Electronics Engineering, VLSI, Microelectronics, Computer Engineering, or related field.