Senior Physical Design Engineer

Samsung Semiconductor; Bengaluru; On-site; INR 2,500,000 - 7,000,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) Bangalore seeks an experienced Senior IC Design Engineer for complex SOC physical implementation across mobile applications, modems and connectivity blocks. You will drive synthesis, placement, routing, STA and sign-off, ensuring timing, power and area targets are met.

The role demands hands-on floorplanning, clock planning, and deep-submicron design expertise, with experience in large SOCs and tape-outs.

Qualifications

• Hands-on experience with physical design and timing closure of complex blocks and full-chip designs.
• Top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning.
• Familiar with deep sub-micron designs (8nm/5nm) and related manufacturability, power and signal integrity issues.
• Experience with large SOC designs (>20M gates) and frequencies >1 GHz.
• Expertise in block-level and full-chip SDC cleanup, synthesis optimization and low-power checking.

Responsibilities

• Complex SOC physical implementation for next-generation mobile application processors, modem subsystems and connectivity chips using Synthesis, Place and Route, STA and physical signoffs.
• Hands-on work on floorplanning, timing, power and area optimization and convergence.
• Debug and resolve LVS/DRC issues at chip/block level; contribute to tape-out readiness.

Skills

Synthesis

Place and Route

STA

Timing closure

Power/Area trade-offs

Perl/Tcl scripting

Education

B.Tech/B.E./M.Tech/M.E

Tools

ICC/DC/PT/VSLP/Redhawk/Calibre/Formality

Job description

With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Roles and Responsibilities

Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs

• Hands on experience doing physical design and timing closure of complex blocks and full-chip des
• igns.Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a
• plus.Should have strong understanding of timing, power and area trade-offs and optimization of
• PPA.Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabili
• ties.Should have solid understanding of scripting languages such as Perl/Tcl and implementation f
• lows.Experience with large SOC designs (>20M gates) with frequencies in excess of 1
• GHZ .Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence chec
• king.Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scal
• ing).Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interact
• ions.Familiar in hierarchical design, top-down design, budgeting, timing and physical converg
• ence.Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
• Should have gone through recent successful SOC tape-outs.

Experience – 5 to 20 Years

Qualifications B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.