Senior PD CAD Engineer

ACL Digital; Hyderabad; On-site; INR 750,000 - 1,100,000; Full time

Job summary

ACL Digital in Hyderabad is seeking a Silicon Design Engineer (CAD) with 3-5 years of experience to join the team. The role focuses on building scalable PPA regression infrastructure, supporting RTL-to-Gate synthesis flows using DC/Genus, and automating metric tracking across advanced technology nodes.

Proficiency in Python/Tcl scripting and Unix environments is essential to drive flow efficiency for timing, area, and power.

Qualifications

• 3-5 years of experience in silicon design CAD/EDA
• Build scalable PPA regression infrastructure
• Support RTL-to-Gate synthesis flows (DC/Genus)
• Automate metric tracking across advanced technology nodes
• Proficient in Python/Tcl scripting and Unix environments

Responsibilities

• Develop and maintain PPA regression infrastructure
• Assist in timing, area and power flow optimization
• Support end-to-end RTL-to-Gate synthesis flows and flow automation

Skills

Python scripting

Tcl scripting

Unix environments

Tools

DC

Genus

Job description

We are Hiring: Silicon Design Engineer - CAD (PPA Regression & Front-End Flow)

ACL Digital is looking for a skilled CAD Engineer with 3-5 years of experience to join our team in Hyderabad. In this role, you will build scalable PPA regression infrastructure, support RTL-to-Gate synthesis flows (DC/Genus), and automate metric tracking across advanced technology nodes. If you excel at Python/Tcl scripting, Unix environments, and driving flow efficiency for timing, area, and power, we want to hear from you!