Harware engineer -2512

Sunrise Biztech Systems; Hyderabad; On-site; INR 900,000 - 1,200,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is hiring a SPW Silicon Design Engineer - CAD (PPA Regression & Front-End Flow) in Hyderabad. The role focuses on PPA regression setup, synthesis and front-end flow support, and automation to improve flow robustness across technology nodes and configurations.

You will work with design, CAD, and methodology teams to diagnose bottlenecks and drive improvements in timing, area, and power metrics while enabling scalable regression infrastructures and tools.

Qualifications

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field.
• 2–3 years of experience in CAD, synthesis/front-end flows, or implementation methodologies.
• Strong foundation in digital design fundamentals and implementation flows.

Responsibilities

• Develop and maintain PPA regression infrastructure across multiple designs, nodes, and flow configurations
• Analyze regression results to identify PPA trends, bottlenecks, and optimization opportunities
• Support Synthesis and Front-End (RTL-to-Gate) flows, including setup, validation, and debug
• Drive automation for flow setup, regression execution, and data collection/reporting
• Collaborate with implementation teams to refine timing, area, and power optimization strategies
• Enable Design of Experiments (DoE) to study impact of tool/flow/technology changes on PPA
• Debug flow issues related to synthesis, constraints, libraries, and methodology changes
• Develop utilities/scripts to improve flow efficiency, reproducibility, and scalability
• Contribute to CAD flow development and methodology improvements for advanced nodes
• Ensure version control, testing, and release management for regression and flow updates

Skills

UNIX/Linux

Python scripting

Tcl

Perl

Shell scripting

Synthesis flows

PPA metrics

Regression frameworks

EDA tools

Git

Debugging

Education

Bachelor’s or Master’s degree in Electronics / Electrical Engineering

Tools

DC/Genus

RTL-to-GDSII

Git

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Hardware design Engineer
Experience:3-5 Years

Location: Hyderabad

Full Time Employment/Contractual

Role & responsibilities

SPW Silicon Design Engineer -CAD (PPA Regression & Front-End Flow)

THE ROLE:

This position is for a CAD/Methodology Engineer focused on Power, Performance, and Area (PPA) regression setup and analysis, along with Synthesis and Front-End flow support. The candidate will play a key role in enabling scalable regression infrastructure, improving front-end implementation methodologies, and ensuring consistent PPA tracking across technology nodes and design configurations.

The role involves close interaction with design, CAD, and methodology teams to enhance flow robustness, debug issues, and optimize implementation quality metrics.

THE PERSON:

You are a highly motivated and detail-oriented engineer with a strong foundation in digital design and implementation flows. You thrive in a collaborative, global environment and are comfortable working across teams and time zones.

You bring strong debugging and analytical skills, a structured problem-solving mindset, and an eagerness to learn and improve design flows. You are passionate about automation, scalability, and driving efficiency in design methodologies.

KEY RESPONSIBILITIES:

• Develop and maintain PPA regression infrastructure across multiple designs, nodes, and flow configurations
• Analyze regression results to identify PPA trends, bottlenecks, and optimization opportunities
• Support Synthesis and Front-End (RTL-to-Gate) flows, including setup, validation, and debug
• Drive automation for flow setup, regression execution, and data collection/reporting
• Collaborate with implementation teams to refine timing, area, and power optimization strategies
• Enable Design of Experiments (DoE) to study impact of tool/flow/technology changes on PPA
• Debug flow issues related to synthesis, constraints, libraries, and methodology changes
• Develop utilities/scripts to improve flow efficiency, reproducibility, and scalability
• Contribute to CAD flow development and methodology improvements for advanced nodes
• Ensure version control, testing, and release management for regression and flow updates

TOOL & TECHNICAL EXPERTISE REQUIRED:

• Strong expertise in UNIX/Linux environments
• Proficiency in scripting languages: Python, Tcl, Perl (mandatory), shell scripting (bash)
• Good understanding of Synthesis flows (e.g., DC/Genus) and front-end implementation concepts
• Familiarity with PPA metrics (timing, power, area) and optimization techniques
• Experience in regression frameworks, automation, and data analysis/reporting
• Exposure to EDA tools and flows in RTL-to-GDSII implementation is highly desirable
• Knowledge of version control systems (e.g., Git), testing, and release processes
• Strong debugging skills across flow, scripts, and tool interactions

ADDED ADVANTAGE:

• Hands-on experience with PnR or back-end flows
• Familiarity with constraint development (SDC), MMMC flows, and library usage
• Exposure to advanced process nodes and low-power methodologies
• Prior experience in PPA optimization or large-scale regression environments

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field
• 2–3 years of experience in CAD, synthesis/front-end flows, or implementation methodologies
• Strong foundation in digital design fundamentals and implementation flows

SOFT SKILLS:

• Strong analytical and problem-solving skills
• Effective communication and collaboration across global teams
• Proactive, self-driven, and willing to take ownership
• Good documentation and organizational skills