Senior Manager Digital Design

Connectpro Management Consultants; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Connectpro Management Consultants in Bengaluru invites a Principal Engineer / Senior Manager Digital Design to drive architecture, RTL design, and development of next-gen UA Link Switch products within the Memory Interface Division.

The role requires leading high-speed digital design initiatives for AI, HPC, and memory-centric systems, mentoring distributed teams, and ensuring silicon readiness from concept to production.

Qualifications

• Experience in ASIC/SoC design and architecture.
• Proficient in RTL design using Verilog/SystemVerilog.
• Strong understanding of NoC, high-speed interconnects, and memory subsystems.

Responsibilities

• Provide technical vision and architectural guidance for UA Link Switch development.
• Lead high-speed digital design initiatives across SoC projects.
• Mentor engineers and drive cross-functional collaboration across teams.

Skills

ASIC/SoC design

RTL Design

SoC architecture

NoC & interconnects

High-speed interconnects

Synthesis & STA

Low-power design

Leadership

Cross-functional collaboration

Job description

Principal Engineer / Senior Manager Digital Design

Location: Bangalore | Experience: 15+ Years

We are looking for an experienced Digital Design Lead to drive the architecture, microarchitecture, RTL design, and development of next-generation UA Link Switch products within the Memory Interface Division (MID). The ideal candidate will bring deep expertise in high-speed digital system design and SoC development, with a proven track record delivering complex silicon products from architecture through production.

The role involves leading high-speed digital design initiatives and delivering scalable, high-bandwidth, low-latency interconnect solutions for AI, HPC, and memory-centric systems.

Key Requirements:

• 15+ years of ASIC/SoC design experience.
• Strong expertise in RTL Design (Verilog/System Verilog), SoC architecture, and subsystem integration.
• Experience with switching fabrics, NoC, high-speed interconnects, memory subsystems, and high-bandwidth data movement architectures.
• Hands-on knowledge in modern ASIC development flows including of synthesis, STA, low-power design methodologies, and silicon bring-up.
• Proven track record leading complex chip development programs from architecture to production and influence cross-functional teams.

Preferred:

• Experience with PCIe, CXL, Ethernet, UCIe, SerDes, AI/HPC interconnects, or memory interface technologies.
• Exposure to large-scale SoCs for networking, compute, storage, or memory applications.
• Strong understanding of system-level architecture and board-level considerations for high-speed designs.
• Strong leadership, mentoring, and cross-functional collaboration skills.
• Experience leading geographically distributed engineering teams.

Leadership Expectations:

• Provide technical vision and architectural guidance for UA Link Switch development.
• Drive innovation in high-bandwidth, low-latency interconnect solutions.
• Mentor and grow engineering talent across the organization.
• Establish engineering best practices and ensure execution excellence across design teams.

Ideal Candidate:

A seasoned digital design leader with deep expertise in high-speed SoC development, switching architectures, and next-generation interconnect technologies, capable of driving complex products from concept to silicon.