Principle Firmware Architect

Connectpro Management Consultants; Bengaluru; On-site; INR 4,200,000 - 6,200,000; Full time

Job summary

Connectpro Management Consultants seeks a Principal Firmware Architect to define end-to-end embedded firmware for UALink switch ASICs in AI cluster scale-up switches. You will bridge silicon and orchestration software, shaping firmware stacks, memory maps, and protocols.

You’ll lead deterministic link training, topology discovery, and security features, partnering with ASIC and RTL teams. Extensive experience in C, RTOS, and high-speed interconnects is required.

Qualifications

• Bachelor’s or higher in Computer Engineering, Electrical Engineering, CS or related.
• 15+ years of hands-on embedded systems/server platform experience.
• Proven expertise in low-level silicon firmware development.

Responsibilities

• Architect and define low-level firmware for UALink switch ASICs.
• Design initialization, boot, and fabric management workflows; develop SDKs and OpenBMC/Redfish interfaces.
• Optimize latency/bandwidth, implement RAS features, and ensure secure boot and attestation.

Skills

C for bare-metal/RTOS

Python for hardware automation

Interconnect protocols (UALink/NVLink/

Firmware architecture

Embedded systems & server platform

Education

Bachelor's/Master’s/Ph.D. in CSE/EE or related

Tools

JTAG

TRACE32 (Lauterbach)

Oscilloscopes

PCIe Protocol Analyzers

Job description

EXP- 15+Location Bangalore

Job description

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches.

In this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators.

1. Architectural Definition & Design

• Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC.
• Hardware-Software Co-Design: Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps.
• Protocol Implementation: Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control.

2. Initialization, Boot, & Fabric Management

• Link Initialization & Training: Design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections.
• Topology Discovery & Routing: Architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion.
• Platform Orchestration: Lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs.

3. Performance, RAS, & Security

• Latency & Bandwidth Optimization: Fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives (e.g., All-Reduce, All-to-All).
• Advanced RAS (Reliability, Availability, Serviceability): Design robust error-handling, telemetry, and fault-isolation micro-architectures (e.g., link degradation fallback, FEC, and error containment).
• Security & Root of Trust: Implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity.

Qualifications

Education & Experience

• Degree: Bachelors or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline.
• Experience: 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.

Technical Skill Set

• Language Masteries: Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling.
• Protocol Expertise: Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6).
• Network Switching Concepts: Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.
• Tooling: Strong familiarity with hardware debuggers (JTAG, Lauterbach Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers).