Senior Lead Engineer - EMIR

Quest Global; Hyderabad; On-site; INR 1,000,000 - 1,800,000; Full time

Job summary

Quest Global is looking for a Senior Lead Engineer in Hyderabad, India, specializing in EMIR (Electromigration & IR Drop Analysis) for semiconductor designs. The role involves leading power integrity analysis, performing static and dynamic analysis, and optimizing complex SoC/ASIC designs. The ideal candidate will have a Bachelor's/Master's in Electronics or similar fields and strong experience with tools like RedHawk and Voltus. Responsibilities include debugging, mentoring junior engineers, and enhancing EMIR methodologies.

Qualifications

• Strong experience in EMIR analysis and power integrity signoff.
• Hands‑on experience with relevant tools such as RedHawk, Voltus, or equivalent.
• Good understanding of physical design flow including floorplanning, placement, routing, and signoff.
• Experience with advanced technology nodes (7nm/5nm/3nm preferred).
• Knowledge of power grid analysis and reliability checks.

Responsibilities

• Lead EMIR analysis and signoff activities for semiconductor designs.
• Perform static and dynamic IR drop analysis and electromigration checks.
• Analyze power integrity issues and provide optimization recommendations.
• Drive technical reviews and mentor junior engineers.

Skills

EMIR analysis

Power integrity signoff

RedHawk

Voltus

Tcl

Perl

Python

Shell scripting

Debugging skills

Analytical problem-solving

Education

Bachelor’s/Master’s degree in Electronics/ECE/VLSI/Microelectronics

Tools

RedHawk

Voltus

Totem

Job description

Role Summary

We are looking for a Senior Lead Engineer with strong expertise in EMIR (Electromigration & IR Drop Analysis) for semiconductor designs. The candidate will be responsible for power integrity analysis, reliability checks, signoff activities, and optimization of complex SoC/ASIC designs across advanced technology nodes.

Key Responsibilities

• Lead EMIR analysis and signoff activities for semiconductor SoC/ASIC designs.
• Perform static and dynamic IR drop analysis and electromigration checks.
• Work closely with PD, floorplanning, power planning, CTS, routing, and package teams.
• Analyze power integrity issues and provide optimization recommendations.
• Debug and resolve EMIR violations to meet signoff requirements.
• Develop and improve EMIR methodologies, flows, and automation scripts.
• Coordinate with foundry and EDA tool teams for issue resolution and best practices.
• Support low-power and high-performance design implementation.
• Drive technical reviews and mentor junior engineers.

Required Skills

• Strong experience in EMIR analysis and power integrity signoff.
• Hands‑on experience with tools such as RedHawk, Voltus, Totem, or equivalent.
• Good understanding of physical design flow including floorplanning, placement, CTS, routing, and signoff.
• Experience with advanced technology nodes (7nm/5nm/3nm preferred).
• Knowledge of power grid analysis, reliability checks, and low‑power methodologies.
• Scripting experience in Tcl, Perl, Python, or Shell.
• Strong debugging, analytical, and problem‑solving skills.

Qualification

• Bachelor’s/Master’s degree in Electronics/ECE/VLSI/Microelectronics or related field.