Senior Implementation Engineer

Arm; Bengaluru; Hybrid; INR 6,000,000 - 12,000,000; Full time

Benefits offered by this job

Hybrid working

Accommodation support

Job summary

Arm in Bengaluru seeks a highly experienced ASIC Physical Design Engineer with 12+ years of hands-on expertise in full-chip and hierarchical SoC physical design. This role requires deep technical knowledge of advanced technology nodes and leadership to drive chip closure from netlist to GDSII.

Responsibilities include leading chip-level floor planning, partitioning, IO/bump planning, power planning, full-chip CTS, and extensive physical verification.

Qualifications

• Chip-level hierarchical floor planning experience.
• Partitioning, partition push-down and IO/Bump planning experience.
• Experience with full-chip integration and analog/digital mixed-signal contexts.

Responsibilities

• Lead chip-level hierarchical floor planning and block-level integration.
• Drive partitioning strategy, partition push-down, and hierarchical design implementation.
• Own pin planning, IO planning, bump planning, and bump routing for complex SoCs.
• Define and execute power planning (ring/mesh/grid architecture, multi-domain handling).
• Perform and manage full-chip CTS and clock architecture optimization.
• Lead chip integration activities across multiple blocks and subsystems.
• Execute and sign off physical verification (DRC, LVS, ERC, ESD, antenna).
• Handle ESD planning and implementation at chip level.
• Drive full-chip closure including congestion, IR/EM, timing, and noise analysis.
• Collaborate with RTL, synthesis, STA, package, and backend teams.
• Support tape-out activities and resolve last-mile issues.
• Mentor junior engineers and provide technical guidance on chip-level challenges.

Skills

Floor planning

Partitioning

Pin planning

IO planning

Bump planning

Power planning

CTS

Physical verification

IR Signoff

Python scripting

EDA tools

Education

B.E./B.Tech in Electrical Engineering

M.S. in Microelectronics

Tools

Innovus

ICC2

Fusion Compiler

Tempus

PrimeTime

Calibre

Job description

We are seeking a highly experienced ASIC Physical Design Engineer with 12+ years of hands‑on expertise in full‑chip and hierarchical SoC physical design.

This role requires deep technical expertise in advanced technology nodes, strong problem‑solving capability, and leadership in driving chip closure from netlist to GDSII.

Responsibilities

Job Overview:

• Lead chip‑level hierarchical floor planning and block‑level integration.
• Drive partitioning strategy , partition push‑down, and hierarchical design implementation.
• Own pin planning, IO planning, bump planning, and bump routing for complex SoCs.
• Define and execute power planning (ring/mesh/grid architecture, multi‑domain handling).
• Perform and manage full‑chip CTS and clock architecture optimization.
• Lead chip integration activities across multiple blocks and subsystems.
• Execute and sign off physical verification (DRC, LVS, ERC, ESD, antenna, etc.).
• Handle ESD planning and implementation at chip level.
• Drive full‑chip closure including congestion, IR/EM, timing, and noise analysis.
• Collaborate closely with RTL, synthesis, STA, package, and backend teams.
• Support tape‑out activities and resolve last‑mile issues.
• Mentor junior engineers and provide technical guidance on chip‑level challenges.

Education

Required Skills and Experience :

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Microelectronics, or related field!

Mandatory Experience

• Chip‑level hierarchical floor planning
• Partitioning & partition push‑down
• Pin planning & IO planning
• Bump planning & bump routing
• ESD planning
• Full‑chip integration
• Physical verification (DRC/LVS/ERC/Antenna), IR DROP, SI‑Noise Signoff.
• Full‑chip CTS
• Power planning (multi‑voltage domains, UPF awareness)
• Hands‑on experience with leading EDA tools (e.g., Innovus, ICC2, Fusion Compiler, Tempus, PrimeTime, Calibre, etc.)
• Experience in advanced nodes (5nm/3nm/2nm or similar preferred)

\"Nice To Have\" Skills And Experience

• Experience leading full‑chip tape‑outs.
• Knowledge of packaging interactions and bump/IO co‑design.
• Ability to script and automate workflows using Python, TCL, or SKILL .
• Familiar with Cadence/Synopsys/Mentor tools

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.