Senior Engineer- Modelling

Arm; Bengaluru; Hybrid; INR 1,800,000 - 2,400,000; Full time

Job summary

Arm’s Physical IP Division develops Physical IP used by SoC designers worldwide to build high-performance chips on advanced nodes. We seek an engineer skilled in ASIC front-end design methodologies to join the Design Enablement team and deploy models for Physical IP including standard cells, embedded memories, and custom blocks.

The role emphasizes model development, validation, automation, and collaboration with EDA vendors.

Qualifications

• Proven experience with ASIC/SoC build flows (simulation, synthesis, DFT, ATPG, LEC) using standard EDA tools.
• Proficient in Verilog and SystemVerilog modeling and verification.
• Strong scripting and automation skills (Python, Tcl, shell, or Perl).
• Ability to learn new technologies quickly and work independently.

Responsibilities

• Model development aligned with IP specifications for Physical IP.
• Validate models in EDA flows and support production deployment.
• Develop robust validation methodologies for model quality.
• Automate model development, validation, and release workflows.
• Improve model quality, performance, and turnaround time.
• Collaborate with engineering groups and EDA vendors to resolve issues.

Skills

ASIC/SoC flows

Verilog/SystemVerilog

Scripting (Python/Tcl)

Automation & debugging

EDA tools knowledge

Problem solving

Team collaboration

Education

Bachelor’s or Master’s in Electronics/Electrical/CE

Tools

Git/Gerrit

CI/CD

EDA tools

Job description

Job Description

Arm’s Physical IP Division develops Physical IP that is extensively used by SoC designers around the world to build sophisticated, high-performance chips on groundbreaking process nodes.

Job Description

Arm’s Physical IP Division develops Physical IP that is extensively used by SoC designers around the world to build sophisticated, high-performance chips on groundbreaking process nodes.

We are seeking a highly skilled and technically proficient engineer with experience in ASIC front-end design methodologies across IP and SoC design domains, to join the Design Enablement team within Solutions Engineering - Implementation organization. The role will focus on developing and deploying models for various types of Physical IP, including standard cells, embedded memories, and custom blocks.

Responsibilities

• Work alongside IP design teams to grasp the functionality and implementation of Physical IP. Coordinate with EDA vendors and SoC design teams to set modeling requirements and specifications.
• Develop models according to specifications, validate them in relevant EDA flows, and deploy and support the models for production use.
• Develop robust validation methodologies to ensure model correctness, quality, and compatibility with downstream design flows.
• Automate model development, validation, and release workflows using scripting and software engineering techniques, including the effective use of LLMs and AI-assisted development tools.
• Continuously improve model quality, performance, development efficiency, and turnaround time.
• Investigate modeling and flow issues and work together with internal groups and EDA vendors to identify and apply solutions.

Vital Skills and Experience

• Solid grasp of ASIC/SoC build flows, particularly simulation, synthesis, Design-for-Test (DFT), ATPG, and logic equivalence checking using industry-standard EDA tools.
• Experience with Verilog and SystemVerilog modeling and verification.
• Good understanding of digital circuit fundamentals, logic composition, and gate-level netlist.
• Strong automation and scripting skills using languages such as Python, Tcl, shell scripting, or Perl.
• Strong analytical and debugging skills, with the ability to investigate complex interactions between models and EDA tools.
• Ability to quickly learn new technologies and methodologies, work independently, and take ownership of new and sophisticated technical issues.
• Capacity to engage successfully with engineering groups spread across different locations and EDA vendors.
• Bachelor’s or Master’s degree or equivalent experience in Electronics, Electrical, Computer Engineering, or a related field, with 5+ years of relevant proven experience.

Preferred Skills and Experience

• Experience with Memory BIST, ATPG, and low-power design methodologies.
• Experience using artificial intelligence techniques for model development and for automating and optimizing engineering workflows.
• Experience with software engineering guidelines, including Git/Gerrit or similar version control systems, test methodologies, continuous integration (CI), and test automation.
• Comfortable working in a fast-paced engineering environment, handling changing priorities, and maintaining a collaborative and positive approach when addressing challenging technical problems.
• Experience collaborating with engineering teams distributed across multiple geographical locations and time zones.

In Return

At Arm, we offer a vibrant, collaborative environment where you will work with colleagues who demonstrate creativity and a strong drive for problem-solving. We are committed to encouraging a diverse and inclusive workspace where everyone feels valued and can contribute to their fullest potential. You will have the opportunity to work on innovative technologies and make a significant impact on the future of semiconductor innovation. Join us and be part of a team that is determined to push the boundaries of what’s possible!

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.