Senior Functional Verification Engineer

Arrow Electronics India Pvt Ltd; Chennai; On-site; INR 800,000 - 1,400,000; Full time

Job summary

Arrow Electronics India Pvt Ltd in Chennai seeks a Senior Engineer (Level 1) for functional verification of SOC/IP blocks using SystemVerilog/UVM. You will develop testbenches, test plans, and verification environments, closing coverage and bugs with a strong debugging mindset.

Requires 4–8 years of hands-on experience, familiarity with Ethernet/PCIe/MIPI/USB/AMBA protocols, and ability to adapt to runtime project changes. Onsite role in Chennai, India.

Qualifications

• 4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM.
• Strong knowledge of UVM, advance UVM,System Verilog .
• Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM.
• Understanding of complete functional verification cycle will be added advantage
• Must have executed at-least 1 to 2 SoC/IP Verification projects.
• Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.
• Skills to debug RTL & testbench issues, test failures.
• Experience on verification closure by closing Coverage and bug reports
• Primarily knowledge of Script development and maintenance
• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc

Responsibilities

• Roles and Responsibilities: 4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM.
• Strong knowledge of UVM, advance UVM,System Verilog.
• Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM.
• Understanding of complete functional verification cycle will be added advantage
• Must have executed at-least 1 to 2 SoC/IP Verification projects.
• Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.
• Skills to debug RTL & testbench issues, test failures.
• Experience on verification closure by closing Coverage and bug reports
• Primarily knowledge of Script development and maintenance
• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc

Skills

SystemVerilog/UVM

UVM knowledge

Testbench development

Bug debugging

Scripting

Verification closure

Job description

Senior Engineer (Level 1) Position: Senior Engineer (Level 1) Job Description: Roles and Responsibilities:

• 4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM.


• Strong knowledge of UVM, advance UVM,System Verilog .


• Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM.

Understanding of complete functional verification cycle will be added advantage

• Must have executed at-least 1 to 2 SoC/IP Verification projects.


• Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.


• Skills to debug RTL & testbench issues, test failures.


• Experience on verification closure by closing Coverage and bug reports


• Primarily knowledge of Script development and maintenance


• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc

Location: IN-TN-Chennai, India-OMR Road (eInfochips)

Time Type: Full time Job Category: Engineering Services Experience Level Senior Level