Senior Engineer- memory compiler flow development

Arm Limited; Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

Arm Limited’s Design Enablement team in Bengaluru is seeking a Senior Software Engineer to build tools for generating physical views of embedded memories using a compiler approach. You will collaborate with Physical IP and SoC design teams and external EDA vendors to define requirements and deliver accurate views for industry-standard flows.

If you bring strong C/C++, Java, Python, shell, and experience with Git/Gerrit, CI, and test automation, plus familiarity with digital circuit concepts and

Qualifications

• 5+ years of relevant industry experience in electronics or computer engineering.
• Proficiency in C/C++, Java, Python, and shell scripting.
• Experience with Git/Gerrit, CI, test automation, and EDA workflows.

Responsibilities

• Develop, improve, and support tools/flows for memory compiler development, focusing on Physical views like GDSII, LEF, NDM, CDL.
• Maintain and improve testing of internal tools and generated views with internal and external EDA tools/flows.
• Automate tool development, validation, and release workflows using scripting and AI-assisted development.

Skills

C/C++

Java

Python

Shell scripting

Git/Gerrit

CI

Test automation

AI/LLM-driven development

Digital circuits

Education

Bachelors/Masters in Electronics/Electrical/Computer Engineering

Tools

Cadence DB

SKILL

GDSII

CDL

Job description

At Arm, we push the boundaries of technology to deliver world-class solutions that build the future of digital innovation. Our Physical IP Division is at the forefront of developing sophisticated, high-performance IPs used by SoC designers globally. Join our Design Enablement team, part of Solutions Engineering - Implementation organization, and be part of an ambitious team working on groundbreaking process nodes!

Job Overview:

We are seeking an exceptionally skilled Senior Software Engineer with a passion for EDA software development. This role focuses on building tools for generating physical views of embedded memories using a compiler approach. Collaborate closely with Physical IP design teams, SoC design teams, and EDA vendors to evaluate methodologies, define new requirements, and develop flawless views for industry-standard EDA flows.

Responsibilities:

• Develop, improve, and support tools/flows for memory compiler development, focusing on Physical views like GDSII, LEF, NDM, CDL, etc.
• Maintain and improve testing of internal tools and generated views using internal and external EDA tools/flows.
• Automate tool development, validation, and release workflows using scripting and software engineering techniques, including the effective use of LLMs and AI-assisted development tools.

Necessary Skills and Experience:

• Proven experience in C/C++, Java, Python, and shell programming with the ability to add significant new functionality, analyze, and fix complex defects.
• Expertise in software engineering guidelines, including Git/Gerrit or similar version control systems, test methodologies, continuous integration (CI), and test automation.
• Familiarity with digital circuit design fundamentals.
• Ability to rapidly grasp new technologies and approaches, work autonomously, and assume responsibility for new and challenging technical problems.
• Experience leveraging AI/LLM-driven techniques for software development and automating engineering workflows.
• Bachelor’s or Master’s degree or equivalent experience in Electronics, Electrical, Computer Engineering, or related fields, with 5+ years of relevant industry experience.

“Preferred” Skills and Experience:

• Experience with circuit & layout design, and formats like CDL, GDSII, LEF, Cadence DB.
• Experience with memory compilers, tiling, netlist stitching, etc.
• Knowledge of EDA flows: Cadence DB, SKILL, place and route, LVS and DRC, extraction, etc.
• Comfortable operating in a dynamic engineering setting, handling shifting priorities, and sustaining a cooperative and optimistic attitude when tackling complex technical issues.
• Experience collaborating with teams distributed across multiple geographical locations and time zones.

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Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.