Senior Engineer- Clock Planning- PD-Full Chip Sub System

Quest Global; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Quest Global in Hyderabad is seeking a seasoned engineer to drive full-chip clock architecture and planning, ensuring scalable distribution, timing robustness, and cross-hierarchy convergence. You will own clock source, hierarchy, partition, and interface planning.

The role requires deep expertise in CTS, full-chip clock planning, and tools like Innovus or ICC2, with experience in large-scale SoC designs. Strong leadership and collaboration with PnR, STA, RTL, and DFT teams are essential.

Qualifications

• Experience in CTS and full-chip clock planning.
• Strong understanding of clock architecture and timing constraints.
• Experience with large-scale SoC designs.
• Proficiency in TCL/Python automation.

Responsibilities

• Own clock source, hierarchy, partition, and interface planning.
• Drive skew, latency, transition, and clock QoR targets.
• Coordinate with PnR, STA, RTL, DFT, and integration teams.
• Lead technical reviews, risk management, and clock closure.

Skills

CTS

Full-chip clock planning

Timing constraints

MCMM analysis

Innovus

ICC2

Leadership

Education

BE/BTech/MTech

Tools

Innovus

ICC2

Job description

Job Description:

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Drive full-chip clock architecture and planning, ensuring scalable distribution, timing robustness, implementation feasibility, and cross-hierarchy convergence.

Key Responsibilities

• Own clock source, hierarchy, partition, and interface planning
• Drive skew, latency, transition, and clock QoR targets
• Coordinate with PnR, STA, RTL, DFT, and integration teams
• Lead technical reviews, risk management, and clock closure

Required Skills & Expertise

Deep expertise in CTS and full-chip clock planning

• Strong understanding of clock architecture, timing constraints, and MCMM analysis
• Innovus or ICC2 expertise
• Experience with advanced-node and large-scale SoC designs
• Strong technical leadership and stakeholder management

Preferred Skills

• Experience with mesh, hybrid, or multi-source clocking
• Exposure to chiplet or multi-die clock integration
• Strong TCL/Python automation capability

Experience

5-7 years

Education

BE/BTech/MTech in Electronics or related field

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.