Senior Engineer- Clock Planning- PD-Full Chip/Sub system

Quest Global; Hyderabad; On-site; INR 1,400,000 - 2,000,000; Full time

Job summary

Quest Global is seeking a senior clock design professional to lead full-chip clock planning and architecture across complex SoCs in Hyderabad, India.

You will own clock sources, hierarchy, and interface planning, while driving QoR targets and coordinating with PnR, STA, RTL and DFT teams. 5–7 years of experience in electronics and advanced-node designs are required.

Qualifications

• Deep expertise in CTS and full-chip clock planning.
• Strong understanding of clock architecture, timing constraints, and MCMM analysis.
• Experience with Innovus or ICC2 and modern SoC designs.
• Experience with large-scale, advanced-node SoC designs.
• Strong technical leadership and stakeholder management.

Responsibilities

• Define clock planning strategy and distribution architecture.
• Own clock source, hierarchy, partition, and interface planning.
• Drive skew, latency, transition, and clock QoR targets.
• Coordinate with PnR, STA, RTL, DFT, and integration teams.
• Lead technical reviews, risk management, and clock closure.

Skills

Clock architecture

CTS expertise

Full-chip clock planning

Timing constraints

MCMM analysis

Leadership

Stakeholder management

SoC designs

Clock QoR targets

Clock synthesis tools

Education

BE/BTech/MTech in Electronics

Tools

Innovus

ICC2

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Drive full-chip clock architecture and planning, ensuring scalable distribution, timing robustness, implementation feasibility, and cross-hierarchy convergence.

Key Responsibilities

• Define clock planning strategy and distribution architecture
• Own clock source, hierarchy, partition, and interface planning
• Drive skew, latency, transition, and clock QoR targets
• Coordinate with PnR, STA, RTL, DFT, and integration teams
• Lead technical reviews, risk management, and clock closure

Required Skills & Expertise

Deep expertise in CTS and full-chip clock planning

• Strong understanding of clock architecture, timing constraints, and MCMM analysis
• Innovus or ICC2 expertise
• Experience with advanced-node and large-scale SoC designs
• Strong technical leadership and stakeholder management

Preferred Skills

• Experience with mesh, hybrid, or multi-source clocking
• Exposure to chiplet or multi-die clock integration
• Strong TCL/Python automation capability

Experience

5-7 years

Education

BE/BTech/MTech in Electronics or related field

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.